View AD9520-5_4266911.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

12 LVPECL/24 CMOS Output Clock Generator AD9520-5
FEATURES
Low phase noise, phase-locked loop (PLL) Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.67 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Auto and manual reference switchover/holdover modes, with selectable revertive/nonrevertive switching Glitch-free switchover between references Automatic recovery from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 1.6 GHz LVPECL outputs divided into 4 groups Each group of 3 has a 1-to-32 divider with phase delay Additive output jitter as low as 225 fs rms Channel-to-channel skew grouped outputs <16 ps Each LVPECL output can be configured as 2 CMOS outputs (for fOUT 250 MHz) Automatic synchronization of all outputs on power-up Manual synchronization of outputs as needed SPI- and IC-compatible serial control port 64-lead LFCSP Nonvolatile EEPROM stores configuration settings
FUNCTIONAL BLOCK DIAGRAM
CP
REFIN
REF2
PLL
REFIN
SWITCHOVER AND MONITOR
REF1
STATUS MONITOR
CLK CLK
DIVIDER AND MUXES
ZERO DELAY LVPECL/ CMOS
DIV/
OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11
DIV/
DIV/
DIV/
Figure 1.
APPLICATIONS
Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures
The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs. Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set. The AD9520 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V. The AD9520 is specified for operation over the standard industrial range of -40C to +85C.
GENERAL DESCRIPTION
The AD9520-51 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO. The AD9520 serial interface supports both SPI and I2C(R) ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.
1
The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-5 is used, it refers to that specific member of the AD9520 family.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07239-001
SPI/I2C CONTROL PORT AND DIGITAL LOGIC
EEPROM
AD9520-5
AD9520-5 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 7 Clock Outputs ............................................................................... 7 Timing Characteristics ................................................................ 8 Timing Diagrams ..................................................................... 9 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ......................... 10 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ............................ 11 Clock Output Additive Time Jitter (VCO Divider Not Used) .......................................................... 11 Clock Output Additive Time Jitter (VCO Divider Used) ..... 12 Serial Control Port--SPI Mode ................................................ 12 Serial Control Port--I2C Mode ................................................ 13 PD, SYNC, and RESET Pins ..................................................... 14 Serial Port Setup Pins: SP1, SP0 ............................................... 14 LD, STATUS, and REFMON Pins ............................................ 14 Power Dissipation ....................................................................... 15 Absolute Maximum Ratings.......................................................... 16 Thermal Resistance .................................................................... 16 ESD Caution ................................................................................ 16 Pin Configuration and Function Descriptions ........................... 17 Typical Performance Characteristics ........................................... 20 Terminology .................................................................................... 24 Detailed Block Diagram ................................................................ 25 Theory of Operation ...................................................................... 26 Operational Configurations ...................................................... 26 Mode 1: Clock Distribution or External VCO < 1600 MHz .................................................. 26 Mode 2: High Frequency Clock Distribution-- CLK or External VCO > 1600 MHz .................................... 28 Phase-Locked Loop (PLL) .................................................... 30 Configuration of the PLL ...................................................... 30 Phase Frequency Detector (PFD) ........................................ 30 Charge Pump (CP)................................................................. 30 PLL External Loop Filter ....................................................... 31 PLL Reference Inputs ............................................................. 31 Reference Switchover ............................................................. 31 Reference Divider R ............................................................... 32 VCO/VCXO Feedback Divider N: P, A, B, R ..................... 32 Digital Lock Detect (DLD) ................................................... 33 Analog Lock Detect (ALD) ................................................... 34 Current Source Digital Lock Detect (CSDLD) .................. 34 External VCXO/VCO Clock Input (CLK/CLK) ................ 34 Holdover .................................................................................. 34 External/Manual Holdover Mode ........................................ 35 Automatic/Internal Holdover Mode.................................... 35 Frequency Status Monitors ................................................... 37 Zero Delay Operation ................................................................ 38 Clock Distribution ..................................................................... 39 Operation Modes ................................................................... 39 CLK Direct-to-LVPECL Outputs......................................... 39 Clock Frequency Division..................................................... 40 VCO Divider ........................................................................... 40 Channel Dividers ................................................................... 40 Synchronizing the Outputs--SYNC Function ................... 42 LVPECL Output Drivers ....................................................... 43 CMOS Output Drivers .......................................................... 44 Reset Modes ................................................................................ 44 Power-On Reset ...................................................................... 44 Hardware Reset via the RESET Pin ..................................... 44 Soft Reset via the Serial Port ................................................. 44 Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via the Serial Port ..................................... 44 Power-Down Modes .................................................................. 44 Chip Power-Down via PD .................................................... 44 PLL Power-Down ................................................................... 45 Distribution Power-Down .................................................... 45 Individual Clock Output Power-Down ............................... 45 Individual Clock Channel Power-Down............................. 45
Rev. 0 | Page 2 of 80
AD9520-5
Serial Control Port ..........................................................................46 SPI/I2C Port Selection ................................................................46 I2C Serial Port Operation ...........................................................46 I2C Bus Characteristics ...........................................................46 Data Transfer Process .............................................................47 Data Transfer Format .............................................................48 I2C Serial Port Timing ............................................................48 SPI Serial Port Operation ...........................................................49 Pin Descriptions ......................................................................49 SPI Mode Operation ...............................................................49 Communication Cycle--Instruction Plus Data ..................49 Write .........................................................................................49 Read ..........................................................................................49 SPI Instruction Word (16 Bits) ..................................................50 SPI MSB/LSB First Transfers .....................................................50 EEPROM Operations......................................................................53 Writing to the EEPROM ............................................................53 Reading from the EEPROM ......................................................53 Programming the EEPROM Buffer Segment.......................... 53 Register Section Definition Group ....................................... 54 IO_UPDATE (Operational Code 0x80) .............................. 54 End-of-Data (Operational Code 0xFF) ............................... 54 Pseudo-End-of-Data (Operational Code 0xFE) ................. 54 Thermal Performance..................................................................... 55 Register Map .................................................................................... 56 Register Map Descriptions ............................................................. 61 Applications Information ............................................................... 75 Frequency Planning Using the AD9520 .................................. 75 Using the AD9520 Outputs for ADC Clock Applications .... 75 LVPECL Clock Distribution ...................................................... 75 CMOS Clock Distribution ......................................................... 76 Outline Dimensions ........................................................................ 77 Ordering Guide ........................................................................... 77
REVISION HISTORY
10/08--Revision 0: Initial Version
Rev. 0 | Page 3 of 80
AD9520-5 SPECIFICATIONS
Typical (typ) is given for VS = VS_DRV = 3.3 V 5%; VS VCP 5.25 V; TA = 25C; RSET = 4.12 k; CPRSET = 5.1 k, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter VS VS_DRV VCP RSET Pin Resistor CPRSET Pin Resistor Min 3.135 2.375 VS Typ 3.3 Max 3.465 VS 5.25 Unit V V V k k Test Conditions/Comments 3.3 V 5% This is nominally 2.5 V to 3.3 V 5% This is nominally 3.3 V to 5.0 V 5% Sets internal biasing currents; connect to ground Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 A); actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground
4.12 5.1
PLL CHARACTERISTICS
Table 2.
Parameter REFERENCE INPUTS Differential Mode (REFIN, REFIN) Input Frequency Input Sensitivity Self-Bias Voltage, REFIN Self-Bias Voltage, REFIN Input Resistance, REFIN Input Resistance, REFIN Dual Single-Ended Mode (REF1, REF2) Input Frequency (AC-Coupled) with DC Offset Off ) Input Frequency (AC-Coupled with DC Offset On) Input Frequency (DC-Coupled) Input Sensitivity (AC-Coupled with DC Offset Off ) Input Sensitivity (AC-Coupled with DC Offset On) Input Logic High, DC Offset Off Input Logic Low, DC Offset Off Input Current Input Capacitance Crystal Oscillator Crystal Resonator Frequency Range Maximum Crystal Motional Resistance PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency Reference Input Clock Doubler Frequency Antibacklash Pulse Width Min Typ Max Unit Test Conditions/Comments Differential mode (can accommodate single-ended input by ac grounding undriven input) Frequencies below about 1 MHz should be dc-coupled; be careful to match VCM (self-bias voltage) Self-bias voltage of REFIN 1 Self-bias voltage of REFIN1 Self-biased1 Self-biased1 Two single-ended CMOS-compatible inputs Slew rate must be > 50 V/s Slew rate must be > 50 V/s, and input amplitude sensitivity specification must be met; see input sensitivity Slew rate > 50 V/s; CMOS levels VIH should not exceed VS VIH should not exceed VS
0 280 1.60 1.50 4.8 5.3
250
MHz mV p-p V V k k MHz MHz MHz V p-p V p-p V V A pF MHz MHz MHz MHz ns ns ns
1.34 1.30 4.0 4.4 10
1.75 1.60 5.9 6.4 250 250
0 0.55 1.5 2.0 -100 2 16.67
250 3.28 2.78
0.8 +100
Each pin, REFIN (REF1)/REFIN (REF2)
33.33 30 100 45 50 1.3 2.9 6.0
0.004
Antibacklash pulse width = 1.3 ns, 2.9 ns Antibacklash pulse width = 6.0 ns Antibacklash pulse width = 1.3 ns, 2.9 ns 0x017[1:0] = 01b 0x017[1:0] = 00b; 0x017[1:0] = 11b 0x017[1:0] = 10b
Rev. 0 | Page 4 of 80
AD9520-5
Parameter CHARGE PUMP (CP) ICP Sink/Source High Value Low Value Absolute Accuracy CPRSET Range ICP High Impedance Mode Leakage Sink-and-Source Current Matching ICP vs. VCP ICP vs. Temperature PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 1 FD P = 2 FD P = 3 FD P = 2 DM (2/3) P = 4 DM (4/5) P = 8 DM (8/9) P = 16 DM (16/17) P = 32 DM (32/33) Prescaler Output Frequency PLL N DIVIDER DELAY 000 001 010 011 100 101 110 111 PLL R DIVIDER DELAY 000 001 010 011 100 101 110 111 PHASE OFFSET IN ZERO DELAY Phase Offset (REF-to-LVPECL Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-LVPECL Clock Output Pins) in Internal Zero Delay Mode Min Typ Max Unit Test Conditions/Comments Programmable With CPRSET = 5.1 k; higher ICP is possible by changing CPRSET With CPRSET = 5.1 k; lower ICP is possible by changing CPRSET Charge pump voltage set to VCP/2
4.8 0.60 2.5 2.7 1 1 1.5 2 10
mA mA % k nA % % %
0.5 V < VCP < VCP - 0.5 V; VCP is the voltage on the CP (charge pump) pin; VCP is the voltage on the VCP power supply pin 0.5 V < VCP < VCP - 0.5 V VCP = VCP/2 V
300 600 900 600 1000 2400 3000 3000 300
MHz MHz MHz MHz MHz MHz MHz MHz MHz
A, B counter input frequency (prescaler input frequency divided by P) Register 0x019[2:0]; see Table 48
Off 410 530 650 770 890 1010 1130 Off 370 490 610 730 850 970 1090 560 -320 1060 +50 1310 +240
ps ps ps ps ps ps ps Register 0x019[5:3]; see Table 48 ps ps ps ps ps ps ps ps ps REF refers to REFIN (REF1)/REFIN (REF2) When N delay and R delay are bypassed When N delay = Setting 110 and R delay is bypassed
Rev. 0 | Page 5 of 80
AD9520-5
Parameter NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) @ 500 kHz PFD Frequency @ 1 MHz PFD Frequency @ 10 MHz PFD Frequency @ 50 MHz PFD Frequency PLL Figure of Merit (FOM) Min Typ Max Unit Test Conditions/Comments The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider) -165 -162 -152 -144 -222 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
PLL DIGITAL LOCK DETECT WINDOW 2
Lock Threshold (Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6.0 ns) Unlock Threshold (Hysteresis)2 Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6.0 ns)
1 2
3.5 7.5 3.5
ns ns ns
7 15 11
ns ns ns
Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is an approximation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed-loop, the phase noise, as observed at the VCO output, is increased by 20 log(N); PLL figure of merit decreases with decreasing slew rate; see Figure 11 Signal available at the LD, STATUS, and REFMON pins when selected by appropriate register settings; lock detect window settings can be varied by changing the CPRSET resistor Selected by 0x017[1:0] and 0x018[4] (this is the threshold to go from unlock to lock) 0x017[1:0] = 00b, 01b,11b; 0x018[4] = 1b 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b 0x017[1:0] = 10b; 0x018[4] = 0b Selected by 0x017[1:0] and 0x018[4] (this is the threshold to go from lock to unlock) 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b 0x017[1:0] = 10b; 0x018[4] = 0b
The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. 0 | Page 6 of 80
AD9520-5
CLOCK INPUTS
Table 3.
Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Min 01 01 150 2 1.3 1.3 3.9 1.57 150 4.7 2 1.8 1.8 5.7 Typ Max 2.4 1.6 Unit GHz GHz mV p-p V p-p V V mV p-p k pF Test Conditions/Comments Differential input High frequency distribution (VCO divider) Distribution only (VCO divider bypassed); this is the frequency range supported by the channel divider Measured at 2.4 GHz; jitter performance is improved with slew rates > 1 V/ns Larger voltage swings can turn on the protection diodes and can degrade jitter performance Self-biased; enables ac coupling With 200 mV p-p signal applied; dc-coupled CLK ac-coupled; CLK ac-bypassed to RF ground Self-biased
Input Sensitivity, Differential Input Level, Differential Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance
1
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9, OUT10, OUT11 Output Frequency, Maximum Min Typ Max Unit Test Conditions/Comments Termination = 50 to VS_DRV - 2 V Differential (OUT, OUT)
2400
MHz
Using direct to output; see Figure 17 (higher frequencies are possible, but amplitude will not meet the VOD specification); the maximum output frequency is limited by the maximum frequency at the CLK inputs
Output High Voltage, VOH Output Low Voltage, VOL Output Differential Voltage, VOD CMOS CLOCK OUTPUTS OUT0A, OUT0B, OUT1A, OUT1B, OUT2A, OUT2B, OUT3A, OUT3B, OUT4A, OUT4B, OUT5A, OUT5B, OUT6A, OUT6B, OUT7A, OUT7B, OUT8A, OUT8B, OUT9A, OUT9B, OUT10A, OUT10B, OUT11A, OUT11B Output Frequency Output Voltage High, VOH Output Voltage Low, VOL Output Voltage High, VOH Output Voltage Low, VOL Output Voltage High, VOH Output Voltage Low, VOL
VS_DRV - 1.07 VS_DRV - 1.95 660
VS_DRV - 0.96 VS_DRV - 1.79 820
VS_DRV - 0.84 VS_DRV - 1.64 950
V V mV Single-ended; termination = 10 pF
250 VS - 0.1 0.1 2.7 0.5 1.8 0.6
MHz V V V V V V
See Figure 18 @ 1 mA load, VS_DRV = 3.3 V/2.5 V @ 1 mA load, VS_DRV = 3.3 V/2.5 V @ 10 mA load, VS_DRV = 3.3 V @ 10 mA load, VS_DRV = 3.3 V @ 10 mA load, VS_DRV = 2.5 V @ 10 mA load, VS_DRV = 2.5 V
Rev. 0 | Page 7 of 80
AD9520-5
TIMING CHARACTERISTICS
Table 5.
Parameter LVPECL OUTPUT RISE/FALL TIMES Output Rise Time, tRP Min Typ 130 Max 170 Unit ps Test Conditions/Comments Termination = 50 to VS_DRV - 2 V 20% to 80%, measured differentially (rise/fall times are independent of VS and are valid for VS_DRV = 3.3 V and 2.5 V) 80% to 20%, measured differentially (rise/fall times are independent of VS and are valid for VS_DRV = 3.3 V and 2.5 V) High frequency clock distribution configuration Clock distribution configuration Termination = 50 to VS_DRV - 2 V VS_DRV = 3.3 V VS_DRV = 2.5 V VS_DRV = 3.3 V VS_DRV = 2.5 V VS_DRV = 3.3 V and 2.5 V Termination = open 20% to 80%; CLOAD = 10 pF; VS_DRV = 3.3 V 80% to 20%; CLOAD = 10 pF; VS_DRV = 3.3 V 20% to 80%; CLOAD = 10 pF; VS_DRV = 2.5 V 80% to 20%; CLOAD = 10 pF; VS_DRV = 2.5 V Clock distribution configuration VS_DRV = 3.3 V VS_DRV = 2.5 V VS_DRV = 3.3 V and 2.5 V VS_DRV = 3.3 V VS_DRV = 2.5 V VS_DRV = 3.3 V VS_DRV = 2.5 V VS_DRV = 3.3 V VS_DRV = 2.5 V All settings identical; different logic type LVPECL to CMOS on same part LVPECL to CMOS on same part
Output Fall Time, tFP
130
170
ps
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT For All Divide Values Variation with Temperature OUTPUT SKEW, LVPECL OUTPUTS 1 LVPECL Outputs That Share the Same Divider LVPECL Outputs on Different Dividers All LVPECL Outputs Across Multiple Parts CMOS OUTPUT RISE/FALL TIMES Output Rise Time, tRC Output Fall Time, tFC Output Rise Time, tRC Output Fall Time, tFC PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT For All Divide Values Variation with Temperature OUTPUT SKEW, CMOS OUTPUTS1 CMOS Outputs That Share the Same Divider All CMOS Outputs on Different Dividers All CMOS Outputs Across Multiple Parts OUTPUT SKEW, LVPECL-TO-CMOS OUTPUT1 Outputs That Share the Same Divider Outputs That Are on Different Dividers
1
850 800
1050 970 1.0 5 5 5 5
1280 1180
ps ps ps/C ps ps ps ps ps ps ps ps ps ns ns ps/C ps ps ps ps ps ps ns ns
16 20 45 60 190 960 890 1280 1100 3.55
750 715 965 890 2.1 2.75 3.35 2 7 10 10 10
85 105 240 285 600 620 2.48 2.50
1.18 1.20
1.76 1.78
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
Rev. 0 | Page 8 of 80
AD9520-5
Timing Diagrams
tCLK
CLK
SINGLE-ENDED
tPECL
80% CMOS 10pF LOAD 20%
07239-060
07239-063
tCMOS
tRC
tFC
Figure 2. CLK/CLK to Clock Output Timing, DIV = 1
DIFFERENTIAL 80% LVPECL 20%
07239-061
Figure 4. CMOS Timing, Single-Ended, 10 pF Load
tRP
tFP
Figure 3. LVPECL Timing, Differential
Rev. 0 | Page 9 of 80
AD9520-5
CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)
Table 6.
Parameter CLK-TO-LVPECL ADDITIVE PHASE NOISE CLK = 1 GHz, Output = 1 GHz Divider = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 100 MHz Offset CLK = 1 GHz, Output = 200 MHz Divider = 5 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK-TO-CMOS ADDITIVE PHASE NOISE CLK = 1 GHz, Output = 250 MHz Divider = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 1 GHz, Output = 50 MHz Divider = 20 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset Min Typ Max Unit Test Conditions/Comments Distribution section only; does not include the PLL Input slew rate > 1 V/ns
-107 -117 -127 -135 -142 -145 -147 -150
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Input slew rate > 1 V/ns
-122 -132 -143 -150 -156 -157 -157
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Distribution section only; does not include the PLL Input slew rate > 1 V/ns
-107 -119 -125 -134 -144 -148 -154
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Input slew rate > 1 V/ns
-126 -133 -140 -148 -157 -160 -163
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Rev. 0 | Page 10 of 80
AD9520-5
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 7.
Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min Typ Max Unit Test Conditions/Comments Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R DIV = 1 Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
54 77 109 79 114 163 124 176 259
fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 8.
Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK = 622.08 MHz Any LVPECL Output = 622.08 MHz Divide Ratio = 1 CLK = 622.08 MHz Any LVPECL Output = 155.52 MHz Divide Ratio = 4 CLK = 1000 MHz Any LVPECL Output = 100 MHz Divide Ratio = 10 CLK = 500 MHz Any LVPECL Output = 100 MHz Divide Ratio = 5 CMOS OUTPUT ADDITIVE TIME JITTER CLK = 200 MHz Any CMOS Output Pair = 100 MHz Divide Ratio = 2 Min Typ Max Unit Test Conditions/Comments Distribution section only; does not include the PLL; measured at rising edge of clock signal Integration bandwidth = 12 kHz to 20 MHz
46
fs rms
64
fs rms
Integration bandwidth = 12 kHz to 20 MHz
223
fs rms
Calculated from SNR of ADC method Broadband jitter Calculated from SNR of ADC method Broadband jitter Distribution section only; does not include the PLL Calculated from SNR of ADC method Broadband jitter
209
fs rms
325
fs rms
Rev. 0 | Page 11 of 80
AD9520-5
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 9.
Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz; Channel Divider = 2; Duty-Cycle Correction = Off CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = On CMOS OUTPUT ADDITIVE TIME JITTER CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = Off CLK = 1600 MHz; VCO DIV = 2; CMOS = 100 MHz; Channel Divider = 8; Duty-Cycle Correction = Off Min Typ Max Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO; uses rising edge of clock signal Calculated from SNR of ADC method (broadband jitter) Calculated from SNR of ADC method (broadband jitter) Distribution section only; does not include PLL; uses rising edge of clock signal Calculated from SNR of ADC method (broadband jitter) Calculated from SNR of ADC method (broadband jitter)
230 215
fs rms fs rms
326 362
fs rms fs rms
SERIAL CONTROL PORT--SPI MODE
Table 10.
Parameter CS (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK (INPUT) IN SPI MODE Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (WHEN AN INPUT IN BIDIRECTIONAL MODE) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO, SDO (OUTPUTS) Output Logic 1 Voltage Output Logic 0 Voltage TIMING Clock Rate (SCLK, 1/tSCLK) Pulse Width High, tHIGH Pulse Width Low, tLOW SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CS to SCLK Setup and Hold, tS, tC CS Minimum Pulse Width High, tPWH 2.0 0.8 110 1 2 2.0 0.8 1 1 2 2.7 0.4 25 16 16 4 0 11 2 3 Min 2.0 0.8 3 -110 2 Typ Max Unit V V A A pF SCLK has an internal 30 k pull-down resistor in SPI mode, but not in I2C mode V V A A pF V V A A pF V V MHz ns ns ns ns ns ns ns Test Conditions/Comments CS has an internal 30 k pull-up resistor
The minus sign indicates that current is flowing out of the AD9520, which is due to the internal pull-up resistor
Rev. 0 | Page 12 of 80
AD9520-5
SERIAL CONTROL PORT--IC MODE
Table 11.
Parameter SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage Input Logic 0 Voltage Input Current with an Input Voltage Between 0.1 x VS and 0.9 x VS Hysteresis of Schmitt Trigger Inputs Pulse Width of Spikes That Must Be Suppressed by the Input Filter, tSPIKE SDA (WHEN OUTPUTTING DATA) Output Logic 0 Voltage at 3 mA Sink Current Output Fall Time from VIHMIN to VILMAX with a Bus Capacitance from 10 pF to 400 pF TIMING Min 0.7 x VS -10 0.015 x VS 50 0.3 x VS +10 Typ Max Unit V V A V ns Test Conditions/Comments
20 + 0.1 Cb
0.4 250
V ns
Cb = capacitance of one bus line in pF Note that all I2C timing values referred to VIHMIN (0.3 x VS) and VILMAX levels (0.7 x VS)
Clock Rate (SCL, fI2C) Bus Free Time Between a Stop and Start Condition, tIDLE Setup Time for a Repeated Start Condition, tSET; STR Hold Time (Repeated) Start Condition (After This Period, the First Clock Pulse Is Generated), tHLD; STR Setup Time for Stop Condition, tSET; STP Low Period of the SCL Clock, tLOW High Period of the SCL Clock, tHIGH SCL, SDA Rise Time, tRISE SCL, SDA Fall Time, tFALL Data Setup Time, tSET; DAT
400 1.3 0.6 0.6 0.6 1.3 0.6 20 + 0.1 Cb 20 + 0.1 Cb 120
kHz s s s s s s ns ns ns
300 300
Data Hold Time, tHLD; DAT
140
880
ns
This is a minor deviation from the original IC specification of 100 ns minimum This is a minor deviation from the original IC specification of 0 ns minimum 1
Capacitive Load for Each Bus Line, Cb
1
400
pF
According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL falling edge.
Rev. 0 | Page 13 of 80
AD9520-5
PD, SYNC, AND RESET PINS
Table 12.
Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low RESET Inactive to Start of Register Programming SYNC TIMING Pulse Width Low Min 2.0 0.8 1 -110 2 50 100 1.3 Typ Max Unit V V A A pF ns ns ns High speed clock is CLK input signal Test Conditions/Comments Each of these pins has a 30 k internal pull-up resistor
The minus sign indicates that current is flowing out of the AD9520, which is due to the internal pull-up resistor
SERIAL PORT SETUP PINS: SP1, SP0
Table 13.
Parameter SP1, SP0 Logic Level 0 Logic Level 1/2 Logic Level 1 Min Typ Max 0.25 x VS 0.65 x VS Unit V V V Test Conditions/Comments These pins do not have internal pull-up/pull-down resistors VS is the voltage on the VS pin User can float these pins to obtain Logic Level 1/2; if floating this pin, user should connect a capacitor to ground
0.4 x VS 0.8 x VS
LD, STATUS, AND REFMON PINS
Table 14.
Parameter OUTPUT CHARACTERISTICS Min Typ Max Unit Test Conditions/Comments When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 48, 0x017, 0x01A, and 0x01B
Output Voltage High, VOH Output Voltage Low, VOL MAXIMUM TOGGLE RATE
2.7 0.4 100
V V MHz
Applies when mux is set to any divider or counter output or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs can couple to output when any of these pins is toggling On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor Frequency above which the monitor indicates the presence of the reference Frequency above which the monitor indicates the presence of the reference
ANALOG LOCK DETECT Capacitance REF1, REF2, AND CLK FREQUENCY STATUS MONITOR Normal Range Extended Range LD PIN COMPARATOR Trip Point Hysteresis
3
pF
1.02 8
MHz kHz
1.6 260
V mV
Rev. 0 | Page 14 of 80
AD9520-5
POWER DISSIPATION
Table 15.
Parameter POWER DISSIPATION, CHIP Min Typ Max Unit Test Conditions/Comments Does not include power dissipated in external resistors; all LVPECL outputs terminated with 50 to VCC - 2 V; all CMOS outputs have 10 pF capacitive loading; VS_DRV = 3.3 V No clock; no programming; default register values fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider = 2; one LVPECL output and output divider enabled; zero delay off fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider bypassed; one LVPECL output and output divider enabled; zero delay off PLL on; VCO divider = 2; all channel dividers on; 12 LVPECL outputs @ 125 MHz; zero delay on PD pin pulled low; does not include power dissipated in termination resistors PD pin pulled low; PLL power-down, 0x010[1:0] = 01b; power-down SYNC, 0x230[2] = 1b; power-down distribution reference, 0x230[1] = 1b PLL operating; typical closed-loop configuration Power delta when a function is enabled/disabled VCO divider not used Delta between reference input off and differential reference input mode Delta between reference inputs off and one singled-ended reference enabled; double this number if both REF1 and REF2 are powered up PLL off to PLL on, normal operation; no reference enabled No LVPECL output on to one LVPECL output on; channel divider set to 1 Second LVPECL output turned on, same channel No CMOS output on to one CMOS output on; channel divider set to 1; fOUT = 62.5 MHz and 10 pF of capacitive loading Additional CMOS outputs within the same channel turned on Delta between divider bypassed (divide-by-1) and divide-by-2 to divide-by-32
Power-On Default Distribution Only Mode; VCO Divider On; One LVPECL Output Enabled Distribution Only Mode; VCO Divider Off; One LVPECL Output Enabled Maximum Power, Full Operation PD Power-Down PD Power-Down, Maximum Sleep
1.32 0.39 0.36 1.4 60 24
1.5 0.46 0.42 1.7 80 33
W W W W mW mW
VCP Supply POWER DELTAS, INDIVIDUAL FUNCTIONS VCO Divider On/Off REFIN (Differential) Off REF1, REF2 (Single-Ended) On/Off
4 32 25 15
4.8 40 30 20
mW mW mW mW
PLL Dividers and Phase Detector On/Off LVPECL Channel LVPECL Driver CMOS Channel CMOS Driver On/Off Channel Divider Enabled Zero Delay Block On/Off
51 121 51 145 11 40 30
63 144 73 180 24 57 34
mW mW mW mW mW mW mW
Rev. 0 | Page 15 of 80
AD9520-5 ABSOLUTE MAXIMUM RATINGS
Table 16.
Parameter or Pin VS VCP, CP VS_DRV REFIN, REFIN RSET CPRSET CLK, CLK CLK SCLK/SCL, SDIO/SDA, SDO, CS OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, OUT9, OUT9, OUT10, OUT10, OUT11, OUT11 SYNC, RESET, PD REFMON, STATUS, LD SP0, SP1, EEPROM Junction Temperature 1 Storage Temperature Range Lead Temperature (10 sec)
1
With Respect to GND GND GND GND GND GND GND CLK GND GND
Rating -0.3 V to +3.6 V -0.3 V to +5.8 V -0.3 V to +3.6 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -1.2 V to +1.2 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
Thermal impedance measurements were taken on a JEDEC JESD51-5 2S2P test board in still air in accordance with JEDEC JESD51-2. See the Thermal Performance section for more details. Table 17.
Package Type 64-Lead LFCSP (CP-64-4) JA 22 Unit C/W
GND GND GND
-0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V 150C -65C to +150C 300C
ESD CAUTION
See Table 17 for JA.
Rev. 0 | Page 16 of 80
AD9520-5 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REFIN (REF1) REFIN (REF2) CPRSET VS VS GND RSET VS OUT0 (OUT0A) OUT0 (OUT0B) VS_DRV OUT1 (OUT1A) OUT1 (OUT1B) OUT2 (OUT2A) OUT2 (OUT2B) VS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VS REFMON LD VCP CP STATUS REF_SEL SYNC NC NC VS VS CLK CLK CS SCLK/SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
AD9520-5
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
OUT3 (OUT3A) OUT3 (OUT3B) VS_DRV OUT4 (OUT4A) OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) VS VS OUT8 (OUT8B) OUT8 (OUT8A) OUT7 (OUT7B) OUT7 (OUT7A) VS_DRV OUT6 (OUT6B) OUT6 (OUT6A)
SDIO/SDA SDO GND SP1 SP0 EEPROM RESET PD OUT9 (OUT9A) OUT9 (OUT9B) VS_DRV OUT10 (OUT10A) OUT10 (OUT10B) OUT11 (OUT11A) OUT11 (OUT11B) VS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTES 1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
Figure 5. Pin Configuration
Table 18. Pin Function Descriptions
Pin No. 1, 11, 12, 32, 40, 41,49, 57, 60, 61 2 3 4 5 6 7 8 Input/ Output I Pin Type Power Mnemonic VS Description 3.3 V Power Pins.
O O I O O I I
3.3 V CMOS 3.3 V CMOS Power Loop filter 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS
REFMON LD VCP CP STATUS REF_SEL SYNC
9, 10 13 14
I I
Differential clock input Differential clock input
NC CLK CLK
Reference Monitor (Output). This pin has multiple selectable outputs. Lock Detect (Output). This pin has multiple selectable outputs. Power Supply for Charge Pump (CP); VS < VCP < 5.0 V. VCP must still be connected to 3.3 V if the PLL is not used. Charge Pump (Output). This pin connects to an external loop filter. This pin can be left unconnected if the PLL is not used. Programmable Status Output. Reference Select. It selects REF1 (low) or REF2 (high). This pin has an internal 30 k pull-down resistor. Manual Synchronization and Manual Holdover. This pin initiates a manual synchronization and is used for manual holdover. Active low. This pin has an internal 30 k pull-up resistor. No Connect. These pins can be left floating. Along with CLK, this pin is the differential input for the clock distribution section. Along with CLK, this pin is the differential input for the clock distribution section. If a single-ended input is connected to the CLK pin, connect a 0.1 F bypass capacitor from CLK to ground.
Rev. 0 | Page 17 of 80
07239-003
AD9520-5
Pin No. 15 16 17 18 19, 59 20 21 22 Input/ Output I I I/O O I I I I Pin Type 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS GND Three-level logic Three-level logic 3.3 V CMOS Mnemonic CS SCLK/SCL SDIO/SDA SDO GND SP1 SP0 EEPROM Description Serial Control Port Chip Select; Active Low. This pin has an internal 30 k pull-up resistor. Serial Control Port Clock Signal. This pin has an internal 30 k pull-down resistor in SPI mode but is high impedance in IC mode. Serial Control Port Bidirectional Serial Data In/Out. Serial Control Port Unidirectional Serial Data Out. Ground Pins. Select SPI or IC as the serial interface port and select the IC slave address in IC mode. Three-level logic. This pin is internally biased for the open logic level. Select SPI or IC as the serial interface port and select the IC slave address in IC mode. Three-level logic. This pin is internally biased for the open logic level. Setting this pin high selects the register values stored in the internal EEPROM to be loaded at reset and/or power-up. Setting this pin low causes the AD9520 to load the hard-coded default register values at power-up/reset. This pin has an internal 30 k pull-down resistor. Chip Reset, Active Low. This pin has an internal 30 k pull-up resistor. Chip Power-Down, Active Low. This pin has an internal 30 k pull-up resistor. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Output Driver Power Supply Pins. As a group, these pins can be set to either 2.5 V or 3.3 V. All four pins must be set to the same voltage. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.
23 24 25 26 27, 35, 46, 54 28 29 30 31 33 34 36 37 38 39 42 43 44 45
I I O O I O O O O O O O O O O O O O O
3.3 V CMOS 3.3 V CMOS LVPECL or CMOS LVPECL or CMOS Power LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS
RESET PD OUT9 (OUT9A) OUT9 (OUT9B) VS_DRV OUT10 (OUT10A) OUT10 (OUT10B) OUT11 (OUT11A) OUT11 (OUT11B) OUT6 (OUT6A) OUT6 (OUT6B) OUT7 (OUT7A) OUT7 (OUT7B) OUT8 (OUT8A) OUT8 (OUT8B) OUT5 (OUT5B) OUT5 (OUT5A) OUT4 (OUT4B) OUT4 (OUT4A)
Rev. 0 | Page 18 of 80
AD9520-5
Pin No. 47 48 50 51 52 53 55 56 58 62 63 Input/ Output O O O O O O O O O O I Pin Type LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS Current set resistor Current set resistor Reference input Reference input GND Mnemonic OUT3 (OUT3B) OUT3 (OUT3A) OUT2 (OUT2B) OUT2 (OUT2A) OUT1 (OUT1B) OUT1 (OUT1A) OUT0 (OUT0B) OUT0 (OUT0A) RSET CPRSET REFIN (REF2) Description Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Distribution Current Set Resistor. Connect a 4.12 k resistor from this pin to GND. Charge Pump Current Set Resistor. Connect a 5.1 k resistor from this pin to GND. This resistor can be omitted if the PLL is not used. Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF2. This pin can be left unconnected when the PLL is not used. Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1.This pin can be left unconnected when the PLL is not used. The exposed die pad must be connected to GND.
64
I
REFIN (REF1)
EPAD
GND
Rev. 0 | Page 19 of 80
AD9520-5 TYPICAL PERFORMANCE CHARACTERISTICS
350 3 CHANNELS--6 LVPECL
5
CURRENT FROM CP PIN (mA)
300
4 PUMP DOWN 3 PUMP UP
CURRENT (mA)
250
3 CHANNELS--3 LVPECL
200
2 CHANNELS--2 LVPECL
2
150 1 CHANNEL--1 LVPECL 100 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz)
1
07239-108
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOLTAGE ON CP PIN (V)
Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off), LVPECL Outputs Terminated 50 to VS_DRV - 2 V
240 220 200
CURRENT (mA)
PFD PHASE NOISE REFERRED TO PFD INPUT (dBc/Hz)
Figure 9. Charge Pump Characteristics @ VCP = 5.0 V
-140
3 CHANNELS--6 CMOS
-145
180 3 CHANNELS--3 CMOS 160 140 2 CHANNELS--2 CMOS 120 100 80 0 50 100 1 CHANNEL--1 CMOS
07239-109
-150
-155
-160
-165
150
200
250
1
10
100
FREQUENCY (MHz)
PFD FREQUENCY (MHz)
Figure 7. Total Current vs. Frequency, CLK-to-Output (PLL Off), CMOS Outputs with 10 pF Load
5
Figure 10. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
-208 -210
CURRENT FROM CP PIN (mA)
4
PUMP DOWN PUMP UP
PLL FIGURE OF MERIT (dBc/Hz)
-212 -214 -216 -218 DIFFERENTIAL INPUT -220 -222 SINGLE-ENDED INPUT
3
2
1
07239-111
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VOLTAGE ON CP PIN (V)
INPUT SLEW RATE (V/ns)
Figure 8. Charge Pump Characteristics @ VCP = 3.3 V
Figure 11. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN
Rev. 0 | Page 20 of 80
07239-114
0
-224
07239-013
-170 0.1
07239-112
0
AD9520-5
3.5 VS_DRV = 3.3V 3.0 2.5 2.0 1.5 1.0 0.5 0 10k VS_DRV = 2.35V VS_DRV = 3.135V VS_DRV = 2.5V
AMPLITUDE (V)
3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0
VOH (V)
1k RESISTIVE LOAD ()
100
07239-118
0
10
20
30
40
50 TIME (ns)
60
70
80
90
100
Figure 12. CMOS Output VOH (Static) vs. RLOAD (to Ground)
1.2
3.2
Figure 15. CMOS Output with 10 pF Load @ 25 MHz
2pF LOAD
0.8
DIFFERENTIAL OUTPUT (V)
2.8 2.4 AMPLITUDE (V) 2.0 1.6 1.2 0.8 10pF LOAD
0.4
0
-0.4
-0.8
0.4 0 0 1 2 3 4 5 TIME (ns) 6 7 8 9 10
0
2
4
6
8
10
12
14
16
18
20
22
24
TIME (ns)
Figure 13. LVPECL Output (Differential) @ 100 MHz
1.0
07239-014
Figure 16. CMOS Output with 2 pF and 10 pF Load @ 250 MHz
2.0
DIFFERENTIAL SWING (V p-p)
0.2
DIFFERENTIAL SWING (V p-p)
0.6
1.8
1.6
-0.2
1.4
-0.6
1.2
07239-015
0
0.5 TIME (ns)
1.0
1.5
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
Figure 14. LVPECL Differential Voltage Swing @ 1600 MHz
Figure 17. LVPECL Differential Voltage Swing vs. Frequency
Rev. 0 | Page 21 of 80
07239-123
-1.0
1.0
07239-019
-1.2
07239-018
AD9520-5
4.0 3.5 3.0 2pF -100
-110
PHASE NOISE (dBc/Hz)
07239-124
AMPLITUDE (V)
2.5 2.0 1.5 1.0 0.5 0 0 100 200 300 400 500 600 700 FREQUENCY (MHz) 10pF 20pF
-120
-130
-140
-150
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 18. CMOS Output Swing vs. Frequency and Capacitive Load
-100
Figure 20. Additive (Residual) Phase Noise, CLK-to-LVPECL @ 1600 MHz, Divide-by-1
-110
-110
-120
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
-120
-130
-130
-140
-140
-150
-150
-160
07239-128
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. Additive (Residual) Phase Noise, CLK-to-LVPECL @ 245.76 MHz, Divide-by-1
Figure 21. Additive (Residual) Phase Noise, CLK-to-CMOS @ 50 MHz, Divide-by-20
Rev. 0 | Page 22 of 80
07239-131
-160 10
-170 10
07239-130
-160 10
AD9520-5
-100 -120
-110
PHASE NOISE (dBc/Hz)
-120
PHASE NOISE (dBc/Hz)
07239-129
-130
-130
-140
-140
-150
-150
100
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. Additive (Residual) Phase Noise, CLK-to-LVPECL @ 200 MHz, Divide-by-5
-100
Figure 24. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) @ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
-110
PHASE NOISE (dBc/Hz)
-120
-130
-140
-150
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 23. Additive (Residual) Phase Noise, CLK-to-CMOS @ 250 MHz, Divide-by-4
Rev. 0 | Page 23 of 80
07239-132
-160 10
07239-135
-160 10
-160 1k
AD9520-5 TERMINOLOGY
Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in decibels) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the signal-to-noise ratio (SNR) and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
Rev. 0 | Page 24 of 80
AD9520-5 DETAILED BLOCK DIAGRAM
REF_SEL VS GND RSET DISTRIBUTION REFERENCE LD REFMON CPRSET VCP REFERENCE SWITCHOVER REF1
PROGRAMMABLE R DELAY
CLOCK DOUBLER
LOCK DETECT
OPTIONAL REFIN
REF2
STATUS BUF
R DIVIDER
STATUS
PLL REFERENCE
HOLD
REFIN AMP STATUS P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP
N DIVIDER ZERO DELAY BLOCK DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK 1 0 DIVIDE BY 1 TO 32 DIGITAL LOGIC EEPROM OUT0 OUT0 STATUS VS_DRV
PD SYNC RESET EEPROM
OUT1 OUT1
OUT2 OUT2
OUT3 SP1 SP0 SERIAL PORT DECODE OUT3 DIVIDE BY 1 TO 32 I2C INTERFACE
OUT4 OUT4
OUT5 OUT5
SCLK/SCL SDIO/SDA SDO CS
OUT6 OUT6 DIVIDE BY 1 TO 32
OUT7 OUT7
OUT8 OUT8
OUT9 OUT9 DIVIDE BY 1 TO 32
OUT10 OUT10
AD9520-5
OUT11
07239-028
OUT11
Figure 25.
Rev. 0 | Page 25 of 80
LVPECL/CMOS OUTPUT
SPI INTERFACE
AD9520-5 THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
The AD9520 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 44 to Table 55). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. When the desired configuration is programmed, the user can store these values in the on-board EEPROM to allow the part to power up in the desired configuration without user intervention. When using the internal PLL with an external VCO < 1600 MHz, the PLL must be turned on. Table 20. Settings for Using Internal PLL with External VCO < 1600 MHz
Register 0x1E1[0] = 1b 0x010[1:0] = 00b Description Bypass the VCO divider as the source for the distribution section PLL normal operation (PLL on) along with other appropriate PLL settings in 0x010 to 0x01E
Mode 1: Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external VCO/VCXO is <1600 MHz, a configuration that bypasses the VCO divider can be used. This is the only difference from Mode 2. Bypassing the VCO divider limits the frequency of the clock source to <1600 MHz (due to the maximum input frequency allowed at the channel dividers).
An external VCO/VCXO requires an external loop filter that must be connected between CP and the tuning pin of the VCO/ VCXO. This loop filter determines the loop bandwidth and stability of the PLL. Make sure to select the proper PFD polarity for the VCO/VCXO being used. Table 21. Setting the PFD Polarity
Register 0x010[7] = 0b 0x010[7] = 1b Description PFD polarity positive (higher control voltage produces higher frequency) PFD polarity negative (higher control voltage produces lower frequency)
Configuration and Register Settings
For clock distribution applications where the external clock is <1600 MHz, the register settings shown in Table 19 should be used. Table 19. Settings for Clock Distribution < 1600 MHz
Register 0x010[1:0] = 01b 0x1E1[0] = 1b 0x1E1[1] = 0b Description PLL asynchronous power-down (PLL off ) Bypass the VCO divider as the source for the distribution section CLK selected as the source
Rev. 0 | Page 26 of 80
AD9520-5
REF_SEL VS GND RSET DISTRIBUTION REFERENCE LD REFMON CPRSET VCP
REFERENCE SWITCHOVER REF1 REF2
OPTIONAL REFIN
STATUS BUF
PLL REFERENCE
R DIVIDER
STATUS
PROGRAMMABLE R DELAY
CLOCK DOUBLER
LOCK DETECT
HOLD
REFIN AMP STATUS P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP
N DIVIDER ZERO DELAY BLOCK DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK 1 0 DIVIDE BY 1 TO 32 DIGITAL LOGIC EEPROM OUT0 OUT0 STATUS VS_DRV
PD SYNC RESET EEPROM
OUT1 OUT1
OUT2 OUT2
OUT3 SP1 SP0 SERIAL PORT DECODE OUT3 DIVIDE BY 1 TO 32 I2C INTERFACE
OUT4 OUT4
OUT5 OUT5
SCLK/SCL SDIO/SDA SDO CS
OUT6 OUT6 DIVIDE BY 1 TO 32
OUT7 OUT7
OUT8 OUT8
OUT9 OUT9 DIVIDE BY 1 TO 32
OUT10 OUT10
AD9520-5
OUT11
07239-031
OUT11
Figure 26. Clock Distribution or External VCO < 1600 MHz (Mode 1)
Rev. 0 | Page 27 of 80
LVPECL/CMOS OUTPUT
SPI INTERFACE
AD9520-5
Mode 2: High Frequency Clock Distribution--CLK or External VCO > 1600 MHz
The AD9520 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/ divide-by-5/divide-by-6). This is a distribution-only mode that allows for an external input up to 2400 MHz (see Table 3). The maximum frequency that can be applied to the channel dividers is 1600 MHz; therefore, higher input frequencies must be divided down before reaching the channel dividers. When the PLL is enabled, this routing also allows the use of the PLL with an external VCO or VCXO with a frequency <2400 MHz. In this configuration, the external VCO/VCXO feeds directly into the prescaler. The register settings shown in Table 22 are the default values of these registers at power-up or after a reset operation. Table 22. Default Register Settings for Clock Distribution Mode
Register 0x010[1:0] = 01b 0x1E0[2:0] = 000b 0x1E1[0] = 0b Description PLL asynchronous power-down (PLL off ) Set VCO divider = 2 Use the VCO divider
When using the internal PLL with an external VCO, the PLL must be turned on. Table 23. Settings When Using an External VCO
Register 0x010[1:0] = 00b 0x010 to 0x01E Description PLL normal operation (PLL on) PLL settings; select and enable a reference input; set R, N (P, A, B), PFD polarity, and ICP according to the intended loop configuration
An external VCO requires an external loop filter that must be connected between CP and the tuning pin of the VCO. This loop filter determines the loop bandwidth and stability of the PLL. Make sure to select the proper PFD polarity for the VCO being used. Table 24. Setting the PFD Polarity
Register 0x010[7] = 0b 0x010[7] = 1b Description PFD polarity positive (higher control voltage produces higher frequency) PFD polarity negative (higher control voltage produces lower frequency)
Rev. 0 | Page 28 of 80
AD9520-5
REF_SEL VS GND RSET DISTRIBUTION REFERENCE LD PROGRAMMABLE R DELAY CLOCK DOUBLER LOCK DETECT PLL REFERENCE REFMON CPRSET VCP
REFERENCE SWITCHOVER REF1 REF2
OPTIONAL REFIN
STATUS BUF
R DIVIDER
STATUS
HOLD
REFIN AMP STATUS P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP
N DIVIDER ZERO DELAY BLOCK DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK 1 0 DIVIDE BY 1 TO 32 DIGITAL LOGIC EEPROM OUT0 OUT0 STATUS VS_DRV
PD SYNC RESET EEPROM
OUT1 OUT1
OUT2 OUT2
OUT3 SP1 SP0 SERIAL PORT DECODE OUT3 DIVIDE BY 1 TO 32 I2C INTERFACE
OUT4 OUT4 LVPECL/CMOS OUTPUT
07239-029
SPI INTERFACE SCLK/SCL SDIO/SDA SDO CS
OUT5 OUT5
OUT6 OUT6 DIVIDE BY 1 TO 32
OUT7 OUT7
OUT8 OUT8
OUT9 OUT9 DIVIDE BY 1 TO 32
OUT10 OUT10
AD9520-5
OUT11 OUT11
Figure 27. High Frequency Clock Distribution or External VCO > 1600 MHz (Mode 2)
Rev. 0 | Page 29 of 80
AD9520-5
Phase-Locked Loop (PLL)
REF_SEL VS GND RSET DISTRIBUTION REFERENCE LD REFMON CPRSET VCP
REFERENCE SWITCHOVER REF1 REF2
OPTIONAL REFIN
STATUS BUF
PLL REFERENCE
R DIVIDER
STATUS
PROGRAMMABLE R DELAY
CLOCK DOUBLER
LOCK DETECT
HOLD
REFIN AMP
STATUS P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP
N DIVIDER ZERO DELAY BLOCK DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK 1 0 FROM CHANNEL DIVIDER 0 STATUS
VS_DRV
07239-064
Figure 28. PLL Functional Block Diagram
The AD9520 includes on-chip PLL blocks that can be used with an external VCO or VCXO to create a complete phase-locked loop. The PLL requires an external loop filter, which usually consists of a small number of capacitors and resistors. The configuration and components of the loop filter help to establish the loop bandwidth and stability of the PLL. The AD9520 PLL is useful for generating clock frequencies from a supplied reference frequency. This includes conversion of reference frequencies to much higher frequencies for subsequent division and distribution. In addition, the PLL can be used to clean up jitter and phase noise on a noisy reference. The exact choice of PLL parameters and loop dynamics is application specific. The flexibility and depth of the AD9520 PLL allow the part to be tailored to function in many different applications and signal environments.
ADIsimCLKTM is a free program that can help with the design and exploration of the capabilities and features of the AD9520, including the design of the PLL loop filter. The AD9516 model found in ADIsimCLK Version 1.2 can also be used for modeling the AD9520 loop filter. It is available at www.analog.com/clocks.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R divider and the N divider and produces an output proportional to the phase and frequency difference between them. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. The antibacklash pulse width is set by 0x017[1:0]. An important limit to keep in mind is the maximum frequency allowed into the PFD. The maximum input frequency into the PFD is a function of the antibacklash pulse setting, as specified in the phase/frequency detector (PFD) parameter in Table 2.
Configuration of the PLL
Configuration of the PLL is accomplished by programming the various settings for the R divider, N divider, PFD polarity, and charge pump current. The combination of these settings determines the PLL loop bandwidth. These are managed through programmable register settings (see Table 44 and Table 48) and by the design of the external loop filter. Successful PLL operation and satisfactory PLL loop performance are highly dependent on proper configuration of the PLL settings, and the design of the external loop filter is crucial to the proper operation of the PLL.
Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors the phase and frequency relationship between its two inputs and tells the CP to pump up or pump down to charge or discharge the integrating node (part of the loop filter). The integrated and filtered CP current is transformed into a voltage that drives the tuning node of the external VCO to move the VCO frequency up or down. The CP can be set (0x010[3:2]) for high impedance (allows holdover operation), for normal operation (attempts to lock the PLL loop), for pump-up, or for pump-down (test modes). The CP current is programmable in eight steps from (nominally) 0.6 mA to 4.8 mA. The exact value of the CP current LSB is set by the CPRSET resistor, which is nominally 5.1 k.
Rev. 0 | Page 30 of 80
AD9520-5
PLL External Loop Filter
An example of an external loop filter for the PLL is shown in Figure 29. A loop filter must be calculated for each desired PLL configuration. The values of the components depend on the VCO frequency, the KVCO, the PFD frequency, the charge pump current, the desired loop bandwidth, and the desired phase margin. The loop filter affects the phase noise, the loop settling time, and the loop stability. A basic knowledge of PLL theory is necessary for understanding loop filter design. ADIsimCLK can help with the calculation of a loop filter according to the application requirements.
AD9520-5
CLK/CLK EXTERNAL VCO/VCXO
In differential mode, the reference input pins are internally selfbiased so that they can be ac-coupled via capacitors. It is possible to dc couple to these inputs. If the differential REFIN is driven by a single-ended signal, the unused side (REFIN) should be decoupled via a suitable capacitor to a quiet ground. Figure 30 shows the equivalent circuit of REFIN.
VS
85k REF1
CP CHARGE PUMP
R2 R1 C1 C2 C3
07239-065
VS 10k REFIN 12k 150
REFIN 10k
150 10k
Figure 29. Example of External Loop Filter for PLL
PLL Reference Inputs
The AD9520 features a flexible PLL reference input circuit that allows a fully differential input, two separate single-ended inputs, or a 16.67 MHz to 33.33 MHz crystal oscillator with an on-chip maintaining amplifier. An optional reference clock doubler can be used to double the PLL reference frequency. The input frequency range for the reference inputs is specified in Table 2. Both the differential and the single-ended inputs are self-biased, allowing for easy ac coupling of input signals. Either a differential or a single-ended reference must be specifically enabled. All PLL reference inputs are off by default. The differential input and the single-ended inputs share two pins, REFIN (REF1) and REFIN (REF2). The desired reference input type is selected and controlled by 0x01C (see Table 44 and Table 48). When the differential reference input is selected, the self-bias level of the two sides is offset slightly to prevent chattering of the input buffer when the reference is slow or missing. The specification for this voltage level can be found in Table 2. The input hysteresis increases the voltage swing required of the driver to overcome the offset. The single-ended inputs can be driven by either a dc-coupled CMOS level signal or an ac-coupled sine wave or square wave. To avoid input buffer chatter when a single-ended, ac-coupled input signal stops toggling, the user can set 0x018[7] to 1b. This shifts the dc offset bias point down 140 mV. To increase isolation and reduce power, each single-ended input can be independently powered down. The differential reference input receiver is powered down when the differential reference input is not selected or when the PLL is powered down. The single-ended buffers power down when the PLL is powered down or when their respective individual power-down registers are set. When the differential mode is selected, the single-ended inputs are powered down.
REF2
VS
85k
Figure 30. REFIN Equivalent Circuit for Non-XTAL Mode
Crystal mode is nearly identical to differential mode. The user enables a maintaining amplifier by setting the Enable XTAL OSC bit, and putting a series resonant, AT fundamental cut crystal across the REFIN/REFIN pins.
Reference Switchover
The AD9520 supports dual single-ended CMOS inputs, as well as a single differential reference input. In the dual single-ended reference mode, the AD9520 supports automatic and manual PLL reference clock switching between REF1 (on Pin REFIN) and REF2 (on Pin REFIN). This feature supports networking and other applications that require redundant references. The AD9520 features a dc offset option in single-ended mode. This option is designed to eliminate the risk of the reference inputs chattering when they are ac-coupled and the reference clock disappears. When using the reference switchover, the single-ended reference inputs should be dc-coupled CMOS levels (with the AD9520 dc offset feature disabled). Alternatively, the inputs can be ac-coupled and the dc offset feature enabled. The user should keep in mind, however, that the minimum input amplitude for the reference inputs is greater when the dc offset is turned on.
Rev. 0 | Page 31 of 80
07239-066
AD9520-5
There are several configurable modes of reference switchover. The switchover can be performed manually or automatically. Manual switchover is performed either through Register 0x01C or by using the REF_SEL pin. The automatic switchover occurs when REF1 disappears. There is also a switchover deglitch feature which ensures that the PLL does not receive rising edges that are far out of alignment with the newly selected reference. There are two automatic reference switchover modes (0x01C): * Prefer REF1. Switch from REF1 to REF2 when REF1 disappears. Return to REF1 from REF2 when REF1 returns. * Stay on REF2. Automatically switch to REF2 when REF1 disappears, but do not switch back to REF1 when it reappears. The reference can be set back to REF1 manually at an appropriate time. In automatic mode, REF1 is monitored by REF2. If REF1 disappears (two consecutive falling edges of REF2 without an edge transition on REF1), REF1 is considered missing. On the next subsequent rising edge of REF2, REF2 is used as the reference clock to the PLL. If 0x01C[3] = 0b (default), when REF1 returns (four rising edges of REF1 without two falling edges of REF2 between the REF1 edges), the PLL reference switches back to REF1. If 0x01C[3] = 1b, the user can control when to switch back to REF1. This is done by programming the part to manual reference select mode (0x01C[4] = 0b) and by ensuring that the registers and/or the REF_SEL pin is set to select the desired reference. Automatic mode can be reenabled when REF1 is reselected. Manual switchover requires the presence of a clock on the reference input that is being switched to or that the deglitching feature be disabled (0x01C[7]).
Prescaler
The prescaler of the AD9520 allows for two modes of operation: a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM) mode where the prescaler divides by P and (P + 1) {2 and 3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes of operation are given in Table 48, 0x016[2:0]. Not all modes are available at all frequencies (see Table 2). When operating the AD9520 in dual modulus mode, P/(P + 1), the equation used to relate the input reference frequency to the VCO output frequency is fVCO = (fREF/R) x (P x B + A) = fREF x N/R However, when operating the prescaler in FD Mode 1, FD Mode 2, or FD Mode 3, the A counter is not used (A = 0) and the equation simplifies to fVCO = (fREF/R) x (P x B) = fREF x N/R When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32. By using combinations of DM and FD modes, the AD9520 can achieve values of N all the way down to N = 1. Table 25 shows how a 10 MHz reference input can be locked to any integer multiple of N. Note that the same value of N can be derived in different ways, as illustrated by the case of N = 12. The user can choose a fixed divide mode P = 2 with B = 6, use the dual modulus mode 2/3 with A = 0, B = 6, or use the dual modulus mode 4/5 with A = 0, B = 3.
A and B Counters
The B counter must be 3 or bypassed, and unlike the R counter, A = 0 is actually zero. The maximum input frequency to the A/B counter is reflected in the maximum prescaler output frequency (~300 MHz) specified in Table 2. This is the prescaler input frequency (external VCO or CLK) divided by P. For example, dual modulus P = 8/9 mode is not allowed if the external VCO frequency is greater than 2400 MHz because the frequency going to the A/B counter is too high. When the AD9520 B counter is bypassed (B = 1), the A counter should be set to zero, and the overall resulting divide is equal to the prescaler setting, P. The possible divide ratios in this mode are 1, 2, 3, 4, 8, 16, and 32. Although manual reset is not normally required, the A/B counters have their own reset bit. Alternatively, the A and B counters can be reset using the shared reset bit of the R, A, and B counters. Note that these reset bits are not self-clearing.
Reference Divider R
The reference inputs are routed to the reference divider, R. R (a 14-bit counter) can be set to any value from 0 to 16,383 by writing to 0x011 and 0x012. (Both R = 0 and R = 1 give divide-by-1.) The output of the R divider goes to one of the PFD inputs to be compared with the VCO frequency divided by the N divider. The frequency applied to the PFD must not exceed the maximum allowable frequency, which depends on the antibacklash pulse setting (see Table 2). The R divider has its own reset. The R divider can be reset using the shared reset bit of the R, A, and B counters. It can also be reset by a SYNC operation.
VCO/VCXO Feedback Divider N: P, A, B, R
The N divider is a combination of a prescaler (P) and two counters, A and B. The total divider value is N = (P x B) + A where P can be 2, 4, 8, 16, or 32.
R, A, and B Counters: SYNC Pin Reset
The R, A, and B counters can be reset simultaneously through the SYNC pin. This function is controlled by 0x019[7:6] (see Table 48). The SYNC pin reset is disabled by default.
Rev. 0 | Page 32 of 80
AD9520-5
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell. These delays can be enabled to allow adjustment of the phase relationship between the PLL reference clock and the VCO or CLK. Each delay is controlled by three bits. The total delay range is about 1 ns. See 0x019 in Table 2 and Table 48. A lock is not indicated until there is a programmable number of consecutive PFD cycles with a time difference less than the lock detect threshold. The lock detect circuit continues to indicate a lock until a time difference greater than the unlock threshold occurs on a single subsequent cycle. For the lock detect to work properly, the period of the PFD frequency must be greater than the unlock threshold. The number of consecutive PFD cycles required for a lock is programmable (0x018[6:5]). Note that it is possible in certain low (<500 Hz) loop bandwidth, high phase margin cases that the DLD can chatter during acquisition, which can cause the AD9520 to automatically enter and exit holdover. To avoid this problem, it is recommended that the user make provisions for a capacitor to ground on the LD pin so that current source digital lock detect (CSDLD) mode can be used.
Digital Lock Detect (DLD)
By selecting the proper output through the mux on each pin, the DLD function is available at the LD, STATUS, and REFMON pins. The digital lock detect circuit indicates a lock when the time difference of the rising edges at the PFD inputs is less than a specified value (the lock threshold). The loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold). Note that the unlock threshold is wider than the lock threshold, which allows some phase error in excess of the lock window to occur without chattering on the lock indicator. The lock detect window timing depends on the value of the CPRSET resistor, as well as three settings: the digital lock detect window bit (0x018[4]), the antibacklash pulse width bit (0x017[1:0], see Table 2), and the lock detect counter (0x018[6:5]). The lock and unlock detection values in Table 2 are for the nominal value of CPRSET = 5.11 k. Doubling the CPRSET value to 10 k doubles the values in Table 2.
Table 25. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N
fREF (MHz) 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
1
R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
P 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 4 4
A X1 X1 X1 X1 X1 X1 0 1 2 1 X1 0 1 X1 0 0 1
B 1 1 3 4 5 3 3 3 3 4 5 5 5 6 6 3 3
N 1 2 3 4 5 6 6 7 8 9 10 10 11 12 12 12 13
fVCO (MHz) 10 20 30 40 50 60 60 70 80 90 100 100 110 120 120 120 130
Mode FD FD FD FD FD FD DM DM DM DM FD DM DM FD DM DM DM
Notes P = 1, B = 1 (bypassed) P = 2, B = 1 (bypassed) P = 1, B = 3 P = 1, B = 4 P = 1, B = 5 P = 2, B = 3 P and P + 1 = 2 and 3, A = 0, B = 3 P and P + 1 = 2 and 3, A = 1, B = 3 P and P + 1 = 2 and 3, A = 2, B = 3 P and P + 1 = 2 and 3, A = 1, B = 4 P = 2, B = 5 P and P + 1 = 2 and 3, A = 0, B = 5 P and P + 1 = 2 and 3, A = 1, B = 5 P = 2, B = 6 P and P + 1 = 2 and 3, A = 0, B = 6 P and P + 1 = 4 and 5, A = 0, B = 3 P and P + 1 = 4 and 5, A = 1, B = 3
X = don't care.
Rev. 0 | Page 33 of 80
AD9520-5
Analog Lock Detect (ALD)
The AD9520 provides an ALD function that can be selected for use at the LD pin. There are two operating modes for ALD: * N-channel open-drain lock detect. This signal requires a pull-up resistor to the positive supply, VS. The output is normally high with short, low going pulses. Lock is indicated by the minimum duty cycle of the low going pulses. P-channel open-drain lock detect. This signal requires a pull-down resistor to GND. The output is normally low with short, high going pulses. Lock is indicated by the minimum duty cycle of the high going pulses. The user can asynchronously enable individual clock outputs only when CSDLD is high. To enable this feature, set the appropriate bits in the enable output on the CSDLD registers (0x0FC and 0x0FD).
AD9520
110A DLD VOUT C LD PIN COMPARATOR
LD
*
The analog lock detect function requires an RC filter to provide a logic level indicating lock/unlock. The ADIsimCLK tool can be used to help the user select the right passive component values for ALD to ensure its correct operation.
VS = 3.3V
Figure 32. Current Source Digital Lock Detect
External VCXO/VCO Clock Input (CLK/CLK)
This differential input is used to drive the AD9520 clock distribution section. This input can receive up to 2.4 GHz. The pins are internally self-biased, and the input signal should be ac-coupled via capacitors.
CLOCK INPUT STAGE VS CLK
AD9520
LD ALD R1
R2
VOUT
C
07239-067
Figure 31. Example of Analog Lock Detect Filter Using N-Channel Open-Drain Driver
CLK 2.5k 5k 5k
07239-032
Current Source Digital Lock Detect (CSDLD)
During the PLL locking sequence, it is normal for the DLD signal to toggle a number of times before remaining steady when the PLL is completely locked and stable. There may be applications where it is desirable to have DLD asserted only after the PLL is solidly locked. This is possible by using the current source digital lock detect function. The current source lock detect provides a current of 110 A when DLD is true and shorts to ground when DLD is false. If a capacitor is connected to the LD pin, it charges at a rate determined by the current source during the DLD true time but is discharged nearly instantly when DLD is false. By monitoring the voltage at the LD pin (top of the capacitor), LD = high happens only after the DLD is true for a sufficiently long time. Any momentary DLD false resets the charging. By selecting a properly sized capacitor, it is possible to delay a lock detect indication until the PLL is stably locked and the lock detect does not chatter. To use current source digital lock detect, do the following: * * * Place a capacitor to ground on the LD pin Set 0x01A[5:0] = 0x04 Enable the LD pin comparator (0x01D[3] = 1)
2.5k
Figure 33. CLK Equivalent Input Circuit
The CLK/CLK input can be used either as a distribution only input (with the PLL off) or as a feedback input for an external VCO/VCXO using the internal PLL.
Holdover
The AD9520 PLL has a holdover function. Holdover is implemented by placing the charge pump in a high impedance state. This function is useful when the PLL reference clock is lost. Holdover mode allows the external VCO to maintain a relatively constant frequency even though there is no reference clock. Without this function, the charge pump is placed into a constant pump-up or pump-down state, resulting in a massive VCO frequency shift. Because the charge pump is placed in a high impedance state, any leakage that occurs at the charge pump output or the VCO tuning node causes a drift of the VCO frequency. This can be mitigated by using a loop filter that contains a large capacitive component because this drift is limited by the current leakage induced slew rate (ILEAK/C) of the VCO control voltage. Both a manual holdover mode, using the SYNC pin, and an automatic holdover mode are provided. To use either function, the holdover function must be enabled (0x01D[0]).
The LD pin comparator senses the voltage on the LD pin, and the comparator output can be made available at the REFMON pin control (0x01B[4:0]) or the STATUS pin control (0x017[7:2]). The internal LD pin comparator trip point and hysteresis are given in Table 14. The voltage on the capacitor can also be sensed by an external comparator connected to the LD pin. In this case, enabling the on-board LD pin comparator is not necessary.
Rev. 0 | Page 34 of 80
07239-068
REFMON OR STATUS
AD9520-5
External/Manual Holdover Mode A manual holdover mode can be enabled that allows the user to place the charge pump into a high impedance state when the SYNC pin is asserted low. This operation is edge sensitive, not level sensitive. The charge pump enters a high impedance state immediately. To take the charge pump out of a high impedance state, take the SYNC pin high. The charge pump then leaves the high impedance state synchronously with the next PFD rising edge from the reference clock. This prevents extraneous charge pump events from occurring during the time between SYNC going high and the next PFD event. This also means that the charge pump stays in a high impedance state if there is no reference clock present. The B counter (in the N divider) is reset synchronously with the charge pump, leaving the high impedance state on the reference path PFD event. This helps align the edges out of the R and N dividers for faster settling of the PLL. Because the prescaler is not reset, this feature works best when the B and R numbers are close because this results in a smaller phase difference for the loop to settle out. When using this mode, the channel dividers should be set to ignore the SYNC pin (at least after an initial SYNC event). If the dividers are not set to ignore the SYNC pin, any time SYNC is taken low to put the part into holdover, the distribution outputs turn off. The channel divider ignore SYNC function is found in 0x191[6], 0x194[6], 0x197[6], and 0x19A[6] for Channel Divider 0, Channel Divider 1, Channel Divider 2, and Channel Divider 3, respectively.
Automatic/Internal Holdover Mode
When enabled, this function automatically puts the charge pump into a high impedance state when the loop loses lock. The assumption is that the only reason the loop loses lock is due to the PLL losing the reference clock; therefore, the holdover function puts the charge pump into a high impedance state to maintain the VCO frequency as close as possible to the original frequency before the reference clock disappeared. A flowchart of the automatic/internal holdover function operation is shown in Figure 34.
Rev. 0 | Page 35 of 80
AD9520-5
PLL ENABLED
NO DLD == LOW
LOOP OUT OF LOCK. DIGITAL LOCK DETECT SIGNAL GOES LOW WHEN THE LOOP LEAVES LOCK AS DETERMINED BY THE PHASE DIFFERENCE AT THE INPUT OF THE PFD.
YES
NO ANALOG LOCK DETECT PIN INDICATES LOCK WAS PREVIOUSLY ACHIEVED. (0x01D[3] = 1; USE LD PIN VOLTAGE WITH HOLDOVER. 0x01D[3] = 0; IGNORE LD PIN VOLTAGE, TREAT LD PIN AS ALWAYS HIGH.)
WAS LD PIN == HIGH WHEN DLD WENT LOW?
YES
HIGH IMPEDANCE CHARGE PUMP YES NO
CHARGE PUMP IS MADE HIGH IMPEDANCE. PLL COUNTERS CONTINUE OPERATING NORMALLY.
REFERENCE EDGE AT PFD?
CHARGE PUMP REMAINS HIGH IMPEDANCE UNTIL THE REFERENCE RETURNS.
YES RELEASE CHARGE PUMP HIGH IMPEDANCE YES
YES TAKE CHARGE PUMP OUT OF HIGH IMPEDANCE. PLL CAN NOW RESETTLE.
NO
DLD == HIGH
Figure 34. Flowchart of Automatic/Internal Holdover Mode
The holdover function senses the logic level of the LD pin as a condition to enter holdover. The signal at LD can be from the DLD, ALD, or current source LD mode (CSDLD). It is possible to disable the LD comparator (0x01D[3]), which causes the holdover function to always sense LD as being high. If DLD is used, it is possible for the DLD signal to chatter while the PLL is reacquiring lock. The holdover function may retrigger, thereby preventing the holdover mode from terminating. Use of the current source lock detect mode is recommended to avoid this situation (see the Current Source Digital Lock Detect (CSDLD) section).
When in holdover mode, the charge pump stays in a high impedance state as long as there is no reference clock present. As in the external holdover mode, the B counter (in the N divider) is reset synchronously with the charge pump leaving the high impedance state on the reference path PFD event. This helps align the edges out of the R and N dividers for faster settling of the PLL and reduces frequency errors during settling. Because the prescaler is not reset, this feature works best when the B and R numbers are close because this results in a smaller phase difference for the loop to settle out.
Rev. 0 | Page 36 of 80
07239-069
WAIT FOR DLD TO GO HIGH. THIS TAKES 5 TO 255 CYCLES (PROGRAMMING OF THE DLD DELAY COUNTER) WITH THE REFERENCE AND FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT THE PFD. THIS ENSURES THAT THE HOLDOVER FUNCTION WAITS FOR THE PLL TO SETTLE AND LOCK BEFORE THE HOLDOVER FUNCTION CAN BE RETRIGGERED.
AD9520-5
After leaving holdover, the loop then reacquires lock, and the LD pin must go high (if 0x01D[3] = 1) before it can reenter holdover. The holdover function always responds to the state of the currently selected reference (0x01C). If the loop loses lock during a reference switchover (see the Reference Switchover section), holdover is triggered briefly until the next reference clock edge at the PFD. The following registers affect the automatic/internal holdover function: * 0x018[6:5]--lock detect counter. This changes how many consecutive PFD cycles with edges inside the lock detect window are required for the DLD indicator to indicate lock. This impacts the time required before the LD pin can begin to charge as well as the delay from the end of a holdover event until the holdover function can be reengaged. 0x018[3]--disable digital lock detect. This bit must be set to 0 to enable the DLD circuit. Internal/automatic holdover does not operate correctly without the DLD function enabled. 0x01A[5:0]--lock detect pin control. Set this to 000100b to put it in the current source lock detect mode if using the LD pin comparator. Load the LD pin with a capacitor of an appropriate value. 0x01D[3]--LD pin comparator enable. 1 = enable; 0 = disable. When disabled, the holdover function always senses the LD pin as high. 0x01D[1]--external holdover control. 0x01D[0]--holdover enable. If holdover is disabled, both external and automatic internal holdover are disabled.
REF_SEL VS GND RSET DISTRIBUTION REFERENCE LD
For example, if the user wants to configure automatic holdover with * * * Automatic reference switchover, prefer REF1. Digital lock detect: five PFD cycles, high range window. Automatic holdover using the LD pin comparator.
The following registers are set (in addition to the normal PLL registers): * * * * * * * * * * 0x018[6:5] = 00b; lock detect counter = five cycles. 0x018[4] = 0b; digital lock detect window = high range. 0x018[3] = 1b; disable DLD normal operation. 0x01A[5:0] = 000100b; program LD pin control to current source lock detect mode. 0x01C[4] = 1b; enable automatic switchover. 0x01C[3] = 0b; prefer REF1. 0x01C[2:1] = 11b; enable REF1 and REF2 input buffers. 0x01D[3] = 1b; enable LD pin comparator. 0x01D[1] = 0b; disable external holdover mode and use automatic/internal holdover mode. 0x01D[0] = 1b; enable holdover.
*
*
Frequency Status Monitors
The AD9520 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency. A diagram showing their location in the PLL is shown in Figure 35. The PLL reference monitors have two threshold frequencies: normal and extended (see Table 14). The reference frequency monitor thresholds are selected in 0x01F.
REFMON CPRSET VCP
*
* *
REFERENCE SWITCHOVER REF1
PROGRAMMABLE R DELAY
CLOCK DOUBLER
LOCK DETECT
OPTIONAL REFIN
REF2
STATUS STATUS BUF
PLL REFERENCE
R DIVIDER
HOLD
REFIN
CLK FREQUENCY STATUS P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP
N DIVIDER ZERO DELAY BLOCK DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK 1 0 FROM CHANNEL DIVIDER 0 STATUS
VS_DRV
07239-070
Figure 35. Reference and VCO Status Monitors
Rev. 0 | Page 37 of 80
AD9520-5
EXTERNAL VCXO
REFIN/ REFIN
R DIVIDER N DIVIDER
R DELAY PFD N DELAY CP
AD9520-5
LOOP FILTER
MUX1
REG 0x01E[1] = 1 INTERNAL ZERO DELAY CLOCK FEEDBACK PATH
DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK/CLK CHANNEL DIVIDER 0 1 0 OUT0 TO OUT2
CHANNEL DIVIDER 1
OUT3 TO OUT5
CHANNEL DIVIDER 2
OUT6 TO OUT8
CHANNEL DIVIDER 3
OUT9 TO OUT11
07239-053
Figure 36. Zero Delay Function
ZERO DELAY OPERATION
Zero delay operation aligns the phase of the output clocks with the phase of the external PLL reference input. The zero delay function of the AD9520-5 is achieved by feeding the output of Channel Divider 0 back to the PLL N divider. In Figure 36, the change in signal routing for zero delay mode is shown in blue. Set Register 0x01E[1] = 1b to select zero delay mode. In the zero delay mode, the output of Channel Divider 0 is routed back to the PLL (N divider) through Mux1 (feedback path shown in blue in Figure 36). The PLL synchronizes the phase/edge of the output of Channel Divider 0 with the phase/edge of the reference input.
Because the channel dividers are synchronized to each other, the outputs of the channel divider are synchronous with the reference input. Both the R delay and the N delay inside the PLL can be programmed to compensate for the propagation delay from the output drivers and PLL components to minimize the phase offset between the clock output and the reference input to achieve zero delay.
Rev. 0 | Page 38 of 80
AD9520-5
PLL PLL
CLK CLK
DIVIDE BY 1, 2, 3, 4, 5, OR 6
CLK CLK
DIVIDE BY 1, 2, 3, 4, 5, OR 6
1
0 CLOCK DISTRIBUTION
1
0 CLOCK DISTRIBUTION
DISTRIBUTION CLOCK
DISTRIBUTION CLOCK
MODE 1 (CLOCK DISTRIBUTION MODE)
MODE 2 (HF CLOCK DISTRIBUTION MODE)
Figure 37. Simplified Diagram of the Two Clock Distribution Operation Modes
CLOCK DISTRIBUTION
A clock channel consists of three LVPECL clock outputs or six CMOS clock outputs that share a common divider. A clock output consists of the drivers that connect to the output pins. The clock outputs have either LVPECL or CMOS at the pins. The AD9520 has four clock channels. Each channel has its own programmable divider that divides the clock frequency applied to its input. The channel dividers can divide by any integer from 1 to 32. The AD9520 features a VCO divider that divides the CLK input by 1, 2, 3, 4, 5, or 6 before going to the individual channel dividers. The VCO divider has two purposes. The first is to limit the maximum input frequency of the channel dividers to 1.6 GHz. The other is to allow the AD9520 to generate even lower frequencies than would be possible with only a simple post divider. The channel dividers allow for a selection of various duty cycles, depending on the currently set division. That is, for any specific division, D, the output of the divider can be set to high for N + 1 input clock cycles and low for M + 1 input clock cycles (where D = N + M + 2). For example, a divide-by-5 can be high for one divider input cycle and low for four cycles, or a divide-by-5 can be high for three divider input cycles and low for two cycles. Other combinations are also possible. The channel dividers include a duty-cycle correction function that can be disabled. In contrast to the selectable duty cycle just described, this function can correct a non-50% duty cycle caused by an odd division. However, this requires that the division be set by M = N + 1. In addition, the channel dividers allow a coarse phase offset or delay to be set. Depending on the division selected, the output can be delayed by up to 15 input clock cycles. For example, if the frequency at the input of the channel divider is 1 GHz, the channel divider output can be delayed by up to 15 ns. The divider outputs can also be set to start high or to start low.
Operation Modes
There are two clock distribution operating modes, and these are shown in Figure 37. It is not necessary to use the VCO divider if the CLK frequency is less than the maximum channel divider input frequency (1600 MHz); otherwise, the VCO divider must be used to reduce the frequency going to the channel dividers. Table 26 shows how the operation modes are selected. 0x1E1[0] selects the channel divider source. Table 26. Operation Modes
Mode 2 1 0x1E1[0] 0 1 VCO Divider Used Not used
CLK Direct-to-LVPECL Outputs It is possible to connect the CLK directly to the LVPECL outputs. However, the LVPECL outputs may not be able to meet the VOD specification in Table 4 above 1600 MHz. To connect the LVPECL outputs directly to the CLK input, the user must select the VCO divider as the source to the distribution section, even if no channel uses it. Table 27. Routing VCO Divider Input Directly to the Outputs
Register Setting 0x1E1[0] = 0b 0x192[1] = 1b 0x195[1] = 1b 0x198[1] = 1b 0x19B[1] = 1b Selection CLK is the source; VCO divider selected Direct-to-output OUT0, OUT1, OUT2 Direct-to-output OUT3, OUT4, OUT5 Direct-to-output OUT6, OUT7, OUT8 Direct-to-output OUT9, OUT10, OUT11
Rev. 0 | Page 39 of 80
07239-054
AD9520-5
Clock Frequency Division
The total frequency division is a combination of the VCO divider (when used) and the channel divider. When the VCO divider is used, the total division from the CLK to the output is the product of the VCO divider (1, 2, 3, 4, 5, and 6) and the division of the channel divider. Table 28 indicates how the frequency division for a channel is set. Table 28. Frequency Division
VCO Divider Setting1 1 to 6 1 to 6 2 to 6 1 VCO divider bypassed VCO divider bypassed
1
be enabled or disabled according to the setting of the disable divider DCC bits. Table 29. Setting DX for the Output Dividers
Divider 0 1 2 3 Low Cycles M 0x190[7:4] 0x193[7:4] 0x196[7:4] 0x199[7:4] High Cycles N 0x190[3:0] 0x193[3:0] 0x196[3:0] 0x199[3:0] Bypass 0x191[7] 0x194[7] 0x197[7] 0x19A[7] Disable Div DCC 0x192[0] 0x195[0] 0x198[0] 0x19B[0]
Channel Divider Setting Don't care 2 to 32 Bypass Bypass Bypass 2 to 32
CLK Directto-Output Setting Enable Disable Disable Disable Don't care Don't care
Resulting Frequency Division 1 (1 to 6) x (2 to 32) (2 to 6) x (1) Output static (illegal state) 1 2 to 32
Channel Frequency Division (0, 1, 2, and 3)
For each channel (where the channel number x is 0, 1, 2, or 3), the frequency division, DX, is set by the values of M and N (four bits each, representing Decimal 0 to Decimal 15), where Number of Low Cycles = M + 1 Number of High Cycles = N + 1 The high and low cycles are cycles of the clock signal currently routed to the input of the channel dividers (VCO divider out or CLK). When a divider is bypassed, DX = 1. Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows each channel divider to divide by any integer from 1 to 32.
The bypass VCO divider (0x1E1[0] = 1) is not the same as VCO divider = 1.
The channel dividers feeding the output drivers contain one 2-to-32 frequency divider. This divider provides for division-by-1 to division-by-32. Division-by-1 is accomplished by bypassing the divider. The dividers also provide for a programmable duty cycle, with optional duty-cycle correction when the divide ratio is odd. A phase offset or delay in increments of the input clock cycle is selectable. The channel dividers operate with a signal at their inputs up to 1600 MHz. The features and settings of the dividers are selected by programming the appropriate setup and control registers (see Table 44 through Table 55).
Duty Cycle and Duty-Cycle Correction
The duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions: * * * * The M and N values for the channel DCC enabled/disabled VCO divider enabled/bypassed The CLK input duty cycle
VCO Divider
The VCO divider provides frequency division between the CLK input and the clock distribution channel dividers. The VCO divider can be set to divide by 1, 2, 3, 4, 5, or 6 (see Table 51, 0x1E0[2:0]). However, when the VCO divider is set to 1, none of the channel output dividers can be bypassed. The VCO divider can also be set to static, which is useful for applications where the only desired output frequency is the CLK input frequency. Making the VCO divider static increases the wide band spurious-free dynamic range (SFDR). An alternative to achieving the same SFDR performance is to set the VCO divider to 1 and enable CLK direct mode.
The DCC function is enabled by default for each channel divider. However, the DCC function can be disabled individually for each channel divider by setting the disable divider DCC bit for that channel. Certain M and N values for a channel divider result in a non50% duty cycle. A non-50% duty cycle can also result with an even division, if M N. The duty-cycle correction function automatically corrects non-50% duty cycles at the channel divider output to 50% duty cycle. Duty-cycle correction requires the following channel divider conditions: * An even division must be set as M = N. * An odd division must be set as M = N + 1. When not bypassed or corrected by the DCC function, the duty cycle of each channel divider output is the numerical value of (N + 1)/(N + M + 2) expressed as a percent.
Channel Dividers
A channel divider drives each group of three LVPECL outputs. There are four channel dividers (0, 1, 2, and 3) driving 12 LVPECL outputs (OUT0 to OUT11). Table 29 gives the register locations used for setting the division and other functions of these dividers. The division is set by the values of M and N. The divider can be bypassed (equivalent to divide-by-1, divider circuit is powered down) by setting the bypass bit. The duty-cycle correction can
Rev. 0 | Page 40 of 80
AD9520-5
The duty cycle at the output of the channel divider for various configurations is shown in Table 30 to Table 33. Table 30. Channel Divider Output Duty Cycle with VCO Divider 1; Input Duty Cycle Is 50%
DX VCO Divider Even N+M+2 Channel divider bypassed Channel divider bypassed Channel divider bypassed Even Odd Output Duty Cycle Disable Div Disable Div DCC = 1 DCC = 0 50% 50%
Table 32. Channel Divider Output Duty Cycle When the VCO Divider Is Enabled and Set to 1
Input Clock Duty Cycle Any 50% x% DX N+M+2 Even Odd Odd Output Duty Cycle Disable Div DCC = 1 Disable Div DCC = 0 50%, requires M = N (N + 1)/ (M + N + 2) 50%, requires M = N + 1 (N + 1)/ (M + N + 2) (N + 1)/ (N + 1 + x%)/(2 x N + 3), (M + N + 2) requires M = N + 1
Odd = 3
33.3%
50%
Odd = 5
40%
50%
Note that the channel divider must be enabled when the VCO divider = 1. Table 33. Channel Divider Output Duty Cycle When the VCO Divider Is Bypassed
Input Clock Duty Cycle Any DX N+M+2 Channel divider bypassed Even Odd Odd Output Duty Cycle Disable Div DCC = 1 Disable Div DCC = 0 Same as input Same as input duty duty cycle cycle (N + 1)/ (M + N + 2) (N + 1)/ (M + N + 2) (N + 1)/ (M + N + 2) 50%, requires M = N 50%, requires M = N + 1 (N + 1 + x%)/(2 x N + 3), requires M = N + 1
Even, odd Even, odd
(N + 1)/(N + M + 2) (N + 1)/(N + M + 2)
50%, requires M=N 50%, requires M=N+1
Table 31. Channel Divider Output Duty Cycle with VCO Divider 1; Input Duty Cycle Is X%
DX VCO Divider Even N+M+2 Channel divider bypassed Channel divider bypassed Channel divider bypassed Even Odd Even Odd Even Odd Output Duty Cycle Disable Div DCC = 1 Disable Div DCC = 0 50% 50%
Any 50% x%
Odd = 3
33.3%
(1 + x%)/3
If the CLK input is routed directly to the output, the duty cycle of the output is the same as the CLK input.
Odd = 5
40%
(2 + x%)/5
Phase Offset or Coarse Time Delay
Each channel divider allows for a phase offset, or a coarse time delay, to be programmed by setting register bits (see Table 34). These settings determine the number of cycles (successive rising edges) of the channel divider input frequency by which to offset, or delay, the rising edge of the output of the divider. This delay is with respect to a nondelayed output (that is, with a phase offset of zero). The amount of the delay is set by five bits loaded into the phase offset (PO) register plus the start high (SH) bit for each channel divider. When the start high bit is set, the delay is also affected by the number of low cycles (M) programmed for the divider. It is necessary to use the SYNC function to make phase offsets effective (see the Synchronizing the Outputs-- Function section). Table 34. Setting Phase Offset and Division
Divider 0 1 2 3
Rev. 0 | Page 41 of 80
Even Even Odd = 3 Odd = 3 Odd = 5 Odd = 5
(N + 1)/ (N + M + 2) (N + 1)/ (N + M + 2) (N + 1)/ (N + M + 2) (N + 1)/ (N + M + 2) (N + 1)/ (N + M + 2) (N + 1)/ (N + M + 2)
50%, requires M = N 50%, requires M = N + 1 50%, requires M = N (3N + 4 + x%)/(6N + 9), requires M = N + 1 50%, requires M = N (5N + 7 + x%)/(10N + 15), requires M = N + 1
Start High (SH) 0x191[4] 0x194[4] 0x197[4] 0x19A[4]
Phase Offset (PO) 0x191[3:0] 0x194[3:0] 0x197[3:0] 0x19A[3:0]
Low Cycles M 0x190[7:4] 0x193[7:4] 0x196[7:4] 0x199[7:4]
High Cycles N 0x190[3:0] 0x193[3:0] 0x196[3:0] 0x199[3:0]
AD9520-5
Let t = delay (in seconds). c = delay (in cycles of clock signal at input to DX). TX = period of the clock signal at the input of the divider, DX (in seconds). = 16 x SH[4] + 8 x PO[3] + 4 x PO[2] + 2 x PO[1] + 1 x PO[0] The channel divide by is set as N = high cycles and M = low cycles. Case 1 For 15, t = x TX c = t/TX = Case 2 For 16, t = ( - 16 + M + 1) x TX c = t/TX By giving each divider a different phase offset, output-to-output delays can be set in increments of the channel divider input clock cycle. Figure 38 shows the results of setting such a coarse offset between outputs.
CHANNEL DIVIDER INPUT 0 1 2 Tx SH = 0 DIVIDER 0 PO = 0 DIVIDER 1 SH = 0 PO = 1 SH = 0 PO = 2 1 x Tx 2 x Tx
07239-071
* * *
Synchronization of the outputs can be executed as part of the chip power-up sequence. The RESET pin is forced low and then released (chip reset). The PD pin is forced low and then released (chip power-down).
The most common way to execute the SYNC function is to use the SYNC pin to perform a manual synchronization of the outputs. This requires a low going signal on the SYNC pin, which is held low and then released when synchronization is desired. The timing of the SYNC operation is shown in Figure 39 (using the VCO divider) and in Figure 40 (the VCO divider is not used). There is an uncertainty of up to one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the AD9520. The pipeline delay from the SYNC rising edge to the beginning of the synchronized output clocking is between 14 cycles and 15 cycles of clock at the channel divider input, plus either one cycle of the VCO divider input (see Figure 39) or one cycle of the channel divider input (see Figure 40), depending on whether the VCO divider is used. Cycles are counted from the rising edge of the signal. In addition, there is an additional 1.2 ns (typical) delay from the SYNC signal to the internal synchronization logic, as well as the propagation delay of the output driver. The driver propagation delay is approximately 100 ps for the LVPECL driver and approximately 1.5 ns for the CMOS driver. Another common way to execute the SYNC function is by setting and resetting the soft SYNC bit at 0x230[0]. Both setting and resetting of the soft SYNC bit require an update all registers (0x232[0] = 1b) operation to take effect. A SYNC operation brings all outputs that have not been excluded (by the ignore SYNC bit) to a preset condition before allowing the outputs to begin clocking in synchronicity. The preset condition takes into account the settings in each of the channel's start high bit and its phase offset. These settings govern both the static state of each output when the SYNC operation is happening and the state and relative phase of the outputs when they begin clocking again upon completion of the SYNC operation. Between outputs and after synchronization, this allows for the setting of phase offsets. The AD9520 differential LVPECL outputs are four groups of three, sharing a channel divider per triplet. In the case of CMOS, each LVPECL differential pair can be configured as two singleended CMOS outputs. The synchronization conditions apply to all of the drivers that belong to that channel divider. Each channel (a divider and its outputs) can be excluded from any SYNC operation by setting the ignore SYNC bit of the channel. Channels that are set to ignore SYNC (excluded channels) do not set their outputs static during a SYNC operation, and their outputs are not synchronized with those of the included channels.
3
4
5
6
7
8
9
10 11 12 13 14 15
CHANNEL DIVIDER OUTPUTS DIV = 4, DUTY = 50%
DIVIDER 2
Figure 38. Effect of Coarse Phase Offset (or Delay)
Synchronizing the Outputs--SYNC Function
The AD9520 clock outputs can be synchronized to each other. Outputs can be individually excluded from synchronization. Synchronization consists of setting the nonexcluded outputs to a preset set of static conditions. These conditions include the divider ratio and phase offsets for a given channel divider. This allows the user to specify different divide ratios and phase offsets for each of the four channel dividers. Releasing the SYNC pin allows the outputs to continue clocking with the preset conditions applied. Synchronization of the outputs is executed in the following ways: * * The SYNC pin is forced low and then released (manual sync). By setting and then resetting any one of the following three bits: the soft SYNC bit (0x230[0]), the soft reset bit (0x000[5] [mirrored]), and the power-down distribution reference bit (0x230[1]).
Rev. 0 | Page 42 of 80
AD9520-5
CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC CHANNEL DIVIDER OUTPUT CLOCKING
INPUT TO VCO DIVIDER
1
INPUT TO CHANNEL DIVIDER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYNC PIN
OUTPUT OF CHANNEL DIVIDER 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
07239-073
Figure 39. SYNC Timing Pipeline Delay When VCO Divider Is Used
CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC CHANNEL DIVIDER OUTPUT CLOCKING
INPUT TO CLK
1
INPUT TO CHANNEL DIVIDER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYNC PIN
OUTPUT OF CHANNEL DIVIDER 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
Figure 40. SYNC Timing Pipeline Delay When VCO Divider Is Not Used
LVPECL Output Drivers
The LVPECL differential voltage (VOD) is selectable (from ~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to Register 0x0FB). The LVPECL outputs have dedicated pins for power supply (VS_DRV), allowing a separate power supply to be used. VS_DRV can be from 2.5 V or from 3.3 V. The LVPECL output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change. Each LVPECL output can be powered down or powered up as needed. Because of the architecture of the LVPECL output stages, there is the possibility of electrical overstress and breakdown under certain power-down conditions. For this reason, the LVPECL outputs have two power-down modes: total power-down and safe power-down.
In total power-down mode, all output drivers are shut off simultaneously. This mode must not be used if there is an external voltage bias network (such as Thevenin equivalent termination) on the output pins that will cause a dc voltage to appear at the powered down outputs. However, total powerdown mode is allowed when the LVPECL drivers are terminated using only pull-down resistors. The total power-down mode is activated by setting 0x230[1]. The primary power-down mode is the safe power-down mode. This mode continues to protect the output devices while powered down. There are three ways to activate safe powerdown mode: individually set the power-down bit for each driver, power down an individual output channel (all of the drivers associated with that channel are powered down automatically), and activate sleep mode.
Rev. 0 | Page 43 of 80
07239-074
AD9520-5
Hardware Reset via the RESET Pin
SW1B SW1A
R2 200
R1 200
N1 N2
QN1 OUT QN2 OUT
SW2 4.4mA
07239-058
RESET, a hard reset (an asynchronous hard reset is executed by briefly pulling RESET low), restores the chip either to the setting stored in EEPROM (the EEPROM pin = 1) or to the on-chip setting (the EEPROM pin = 0). A hard reset also executes a SYNC operation, which brings the outputs into phase alignment according to the default settings. When EEPROM is inactive (the EEPROM pin = 0), it takes ~2 s for the outputs to begin toggling after RESET is issued. When EEPROM is active (the EEPROM pin = 1), it takes ~20 ms for the outputs to toggle after RESET is brought high.
Figure 41. LVPECL Output Simplified Equivalent Circuit
Soft Reset via the Serial Port
The serial port control register allows for a soft reset by setting Bit 2 and Bit 5 in Register 0x000. When Bit 5 and Bit 2 are set, the chip enters a soft reset mode and restores the chip either to the setting stored in EEPROM (the EEPROM pin = 1) or to the on-chip setting (the EEPROM pin = 0), except for Register 0x000. Except for the self-clearing bits, Bit 2 and Bit 5, Register 0x000 retains its previous value prior to reset. During the internal reset, the outputs hold static. These bits are self-clearing. However, the self-clearing operation does not complete until an additional serial port SCLK cycle, and the AD9520 is held in reset until that happens.
CMOS Output Drivers
The user can also individually configure each LVPECL output as a pair of CMOS outputs, which provides up to 24 CMOS outputs. When an output is configured as CMOS, CMOS Output A and CMOS Output B are automatically turned on. For a given differential pair, either CMOS Output A or Output B can be turned on or off independently. The user can also select the relative polarity of the CMOS outputs for any combination of inverting and noninverting (see Register 0x0F0 to Register 0x0FB). The user can power down each CMOS output as needed to save power. The CMOS output power-down is individually controlled by the enable CMOS output register (0x0F0[6:5] to 0x0FB[6:5]). The CMOS driver is in tristate when it is powered down.
VS_DRV
Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via the Serial Port
The serial port control register allows the chip to be reset to settings in EEPROM when the EEPROM pin = 1 via 0xB02[1]. This bit is self-clearing. This bit does not have any effect when the EEPROM pin = 0. It takes ~20 ms for the outputs to begin toggling after the Soft_EEPROM register is cleared.
OUT1/ OUT1
07239-035
POWER-DOWN MODES
Chip Power-Down via PD
The AD9520 can be put into a power-down condition by pulling the PD pin low. Power-down turns off most of the functions and currents inside the AD9520. The chip remains in this power-down state until PD is brought back to logic high. When taken out of power-down mode, the AD9520 returns to the settings programmed into its registers prior to the power-down, unless the registers are changed by new programming while the PD pin is held low. Powering down the chip shuts down the currents on the chip, except for the bias current necessary to maintain the LVPECL outputs in a safe shutdown mode. The LVPECL bias currents are needed to protect the LVPECL output circuitry from damage that can be caused by certain termination and load configurations when tristated. Because this is not a complete power-down, it can be called sleep mode. The AD9520 contains special circuitry to prevent runt pulses on the outputs when the chip is entering or exiting sleep mode.
Figure 42. CMOS Equivalent Output Circuit
RESET MODES
The AD9520 has a power-on reset (POR) and several other ways to apply a reset condition to the chip.
Power-On Reset
During chip power-up, a power-on reset pulse is issued when VS reaches ~2.6 V (<2.8 V) and restores the chip either to the setting stored in EEPROM (with the EEPROM pin = 1) or to the on-chip setting (with the EEPROM pin = 0). At power-on, the AD9520 also executes a SYNC operation, which brings the outputs into phase alignment according to the default settings. The output drivers are held in sync for the duration of the internally generated power-up sync timer (~70 ms). The outputs begin to toggle after this period.
Rev. 0 | Page 44 of 80
AD9520-5
When the AD9520 is in a PD power-down, the chip is in the following state: * * * * * * * * The PLL is off (asynchronous power-down). The CLK input buffer is off, but the CLK input dc bias circuit is on. In differential mode, the reference input buffer is off, but the dc bias circuit is still on. In singled-ended mode, the reference input buffer is off, and the dc bias circuit is off. All dividers are off. All CMOS outputs are tristated. All LVPECL outputs are in safe off mode. The serial control port is active, and the chip responds to commands.
Distribution Power-Down
The distribution section can be powered down by writing 0x230[1] = 1b, which turns off the bias to the distribution section. If the LVPECL power-down mode is normal operation (0b), it is possible for a low impedance load on that LVPECL output to draw significant current during this power-down. If the LVPECL power-down mode is set to 1b, the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down into safe power-down mode by individually writing to the appropriate registers. The register map details the individual power-down settings for each output. These settings are found in Register 0x0F0[0] to Register 0x0FB[0].
PLL Power-Down
The PLL section of the AD9520 can be selectively powered down. There are two PLL power-down modes set by Register 0x010[1:0]: asynchronous and synchronous. In asynchronous power-down mode, the device powers down as soon as the registers are updated. In synchronous power-down mode, the PLL power-down is gated by the charge pump to prevent unwanted frequency jumps. The device goes into powerdown on the occurrence of the next charge pump event after the registers are updated.
Individual Clock Channel Power-Down
Any of the clock distribution channels can be powered down individually by writing to the appropriate registers. Powering down a clock channel is similar to powering down an individual driver, but it saves more power because the dividers are also powered down. Powering down a clock channel also automatically powers down the drivers connected to it. The register map details the individual power-down settings for each output channel. These settings are found in 0x192[2], 0x195[2], 0x198[2], and 0x19B[2].
Rev. 0 | Page 45 of 80
AD9520-5 SERIAL CONTROL PORT
The AD9520 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9520 serial control port is compatible with most synchronous transfer formats, including Philips I2C, Motorola(R) SPI(R), and Intel(R) SSR protocols. The AD9520 I2C implementation deviates from the classic I2C specification on two specifications, and these deviations are documented in Table 11 of this data sheet. The serial control port allows read/write access to all registers that configure the AD9520.
I2C Bus Characteristics
Table 36. I2C Bus Definitions
Abbreviation S Sr P A A W R Definition Start Repeated start Stop Acknowledge No acknowledge Write Read
SPI/IC PORT SELECTION
The AD9520 has two serial interfaces, SPI and I2C. Users can select either SPI or I2C depending on the states of the three logic level (high, open, low) input pins, SP1 and SP0. When both SP1 and SP0 are high, the SPI interface is active. Otherwise, I2C is active with eight different I2C slave address (seven bits wide) settings, see Table 35. The four MSBs of the slave address are hardware coded as 1011, and the three LSBs are programmed by SP1 and SP0. Table 35. Serial Port Mode Selection
SP1 Low Low Low Open Open Open High High High SP0 Low Open High Low Open High Low Open High Address IC, 1011000 IC, 1011001 IC, 1011010 IC, 1011011 IC, 1011100 IC, 1011101 IC, 1011110 IC, 1011111 SPI
One pulse on the SCL clock line is generated for each data bit transferred. The data on the SDA line must not change during the high period of the clock. The state of the data line can change only when the clock on the SCL line is low.
DATA LINE STABLE; DATA VALID SDA CHANGE OF DATA ALLOWED
SCL
Figure 43. Valid Bit Transfer
A start condition is a transition from high to low on the SDA line while SCL is high. The start condition is always generated by the master to initialize the data transfer. A stop condition is a transition from low to high on the SDA line while SCL is high. The stop condition is always generated by the master to end the data transfer.
SDA
IC SERIAL PORT OPERATION
The AD9520 I2C port is based on the I2C fast mode standard. The AD9520 supports both I2C protocols: standard mode (100 kHz) and fast mode (400 kHz). The AD9520 I2C port has a 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). In an I2C bus system, the AD9520 is connected to the serial bus (data bus SDA and clock bus SCL) as a slave device, meaning that no clock is generated by the AD9520. The AD9520 uses direct 16-bit (two bytes) memory addressing instead of traditional 8-bit (one byte) memory addressing.
SCL S START CONDITION P STOP CONDITION
07239-161
Figure 44. Start and Stop Conditions
A byte on the SDA line is always eight bits long. An acknowledge bit must follow every byte. Bytes are sent MSB first. The acknowledge bit is the ninth bit attached to any 8-bit data byte. An acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. It is done by pulling the SDA line low during the ninth clock pulse after each 8-bit data byte.
Rev. 0 | Page 46 of 80
07239-160
AD9520-5
SDA MSB ACKNOWLEDGE FROM SLAVE-RECEIVER ACKNOWLEDGE FROM SLAVE-RECEIVER
07239-162 07239-164 07239-163
SCL S
1
2
3 TO 7
8
9
1
2
3 TO 7
8
9
10 P
Figure 45. Acknowledge Bit
SDA MSB = 0 ACKNOWLEDGE FROM SLAVE-RECEIVER ACKNOWLEDGE FROM SLAVE-RECEIVER
SCL S
1
2
3 TO 7
8
9
1
2
3 TO 7
8
9
10 P
Figure 46. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)
SDA
MSB = 1 ACKNOWLEDGE FROM MASTER-RECEIVER NO ACKNOWLEDGE FROM SLAVE-RECEIVER 2 3 TO 7 8 9 10 P
SCL S
1
2
3 TO 7
8
9
1
Figure 47. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)
The no acknowledge bit is the ninth bit attached to any 8-bit data byte. A no acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received. It is done by leaving the SDA line high during the ninth clock pulse after each 8-bit data byte.
Data Transfer Process
The master initiates data transfer by asserting a start condition. This indicates that a data stream follows. All I2C slave devices connected to the serial bus respond to the start condition. The master then sends an 8-bit address byte over the SDA line, consisting of a 7-bit slave address (MSB first) plus an R/W bit. This bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, the master (transmitter) writes to the slave device (receiver). If the R/W bit is 1, the master (receiver) reads from the slave device (transmitter). The format for these commands is described in the Data Transfer Format section.
Data is then sent over the serial bus in the format of nine clock pulses, one data byte (8-bit) from either master (write mode) or slave (read mode), followed by an acknowledge bit from the receiving device. The number of bytes that can be transmitted per transfer is unrestricted. In write mode, the first two data bytes immediately after the slave address byte are the internal memory (control registers) address bytes with the high address byte first. This addressing scheme gives a memory address up to 216 - 1 = 65,535. The data bytes after these two memory address bytes are register data written into the control registers. In read mode, the data bytes after the slave address byte are register data read from the control registers. When all data bytes are read or written, stop conditions are established. In write mode, the master (transmitter) asserts a stop condition to end data transfer during the (10th) clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). In read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull it low during the ninth clock pulse. This is known as a no acknowledge bit. By receiving the no acknowledge bit, the slave device knows that the data transfer is finished and releases the SDA line. The master then takes the data line low during the low period before the 10th clock pulse and high during the 10th clock pulse to assert a stop condition. A repeated start (Sr) condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded.
Rev. 0 | Page 47 of 80
AD9520-5
Data Transfer Format
Send byte format--the send byte protocol is used to set up the register address for subsequent commands.
S Slave Address W A RAM Address High Byte A RAM Address Low Byte A P
Write byte format--the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
S Slave Address W A RAM Address High Byte A RAM Address Low Byte A RAM Data 0 A RAM Data 1 A RAM Data 2 A P
Receive byte format--the receive byte protocol is used to read the data byte(s) from RAM starting from the current address.
S Slave Address R A RAM Data 0 A RAM Data 1 A RAM Data 2 A P
Read byte format--the combined format of the send byte and the receive byte.
S Slave Address W A RAM Address High Byte A RAM Address Low Byte A Sr Slave Address R A RAM Data 0 A RAM Data 1 A RAM Data 2 A P
IC Serial Port Timing
SDA
tFALL
SCL
tSET; DAT tLOW tRISE
tFALL
tHLD; STR
tSPIKE
tRISE
tIDLE
S
tHLD; DAT
tHIGH
Sr
P
S
Figure 48. IC Serial Port Timing
Table 37. I2C Timing Definitions
Parameter fI2C tIDLE tHLD; STR tSET; STR tSET; STP tHLD; DAT tSET; DAT tLOW tHIGH tRISE tFALL tSPIKE Description IC clock frequency Bus idle time between stop and start conditions Hold time for repeated start condition Setup time for repeated start condition Setup time for stop condition Hold time for data Setup time for data Duration of SCL clock low Duration of SCL clock high SCL/SDA rise time SCL/SDA fall time Voltage spike pulse width that must be suppressed by the input filter
Rev. 0 | Page 48 of 80
07239-165
tHLD; STR
tSET; STR
tSET; STP
AD9520-5
SPI SERIAL PORT OPERATION
Pin Descriptions
SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. This pin is internally pulled down by a 30 k resistor to ground. SDIO (serial data input/output) is a dual-purpose pin and acts either as an input only (unidirectional mode) or as an input/ output (bidirectional mode). The AD9520 defaults to the bidirectional I/O mode (0x000[7] = 0b). SDO (serial data out) is used only in the unidirectional I/O mode (0x000[7]) as a separate output pin for reading back data. CS (chip select bar) is an active low control that gates the read and write cycles. When CS is high, SDO and SDIO are in a high impedance state. This pin is internally pulled up by a 30 k resistor to VS.
CS SCLK/SCL SDIO/SDA SDO
15 16 17 18
In the streaming mode (see Table 38), any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented (see the SPI MSB/LSB First Transfers section). CS must be raised at the end of the last byte to be transferred, thereby ending streaming mode.
Communication Cycle--Instruction Plus Data
There are two parts to a communication cycle with the AD9520. The first part writes a 16-bit instruction word into the AD9520, coincident with the first 16 SCLK rising edges. The instruction word provides the AD9520 serial control port with information regarding the data transfer, which is the second part of the communication cycle. The instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part is the transfer of data into the serial control port buffer of the AD9520. Data bits are registered on the rising edge of SCLK. The length of the transfer (one, two, or three bytes or streaming mode) is indicated by two bits (W1:W0) in the instruction byte. When the transfer is one, two, or three bytes, but not streaming, CS can be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). When the bus is stalled, the serial transfer resumes when CS is lowered. Raising the CS pin on a nonbyte boundary resets the serial control port. During a write, streaming mode does not skip over reserved or blank registers, and the user can write 0x00 to the reserved register addresses. Because data is written into a serial control port buffer area, not directly into the actual control registers of the AD9520, an additional operation is needed to transfer the serial control port buffer contents to the actual control registers of the AD9520, thereby causing them to become active. The update registers operation consists of setting 0x232[0] = 1b (this bit is selfclearing). Any number of bytes of data can be changed before executing an update registers. The update registers simultaneously actuates all register changes that have been written to the buffer since any previous update.
AD9520
07239-036
SERIAL CONTROL PORT
Figure 49. Serial Control Port
SPI Mode Operation
In SPI mode, single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9520 serial control port can be configured for a single bidirectional I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/ SDO). By default, the AD9520 is in bidirectional mode. Short instruction mode (8-bit instruction) is not supported. Only long (16-bit) instruction mode is supported. A write or a read operation to the AD9520 is initiated by pulling CS low. The CS stalled high mode is supported in data transfers where three or fewer bytes of data (plus instruction data) are transferred (see Table 38). In this mode, the CS pin can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. CS can go high on byte boundaries only and can go high during either part (instruction or data) of the transfer. During this period, the serial control port state machine enters a wait state until all data is sent. If the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset by either completing the remaining transfers or by returning CS low for at least one complete SCLK cycle (but fewer than eight SCLK cycles). Raising the CS pin on a nonbyte boundary terminates the serial transfer and flushes the buffer.
Read
The AD9520 supports only the long instruction mode. If the instruction word is for a read operation, the next N x 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1 to 3 as determined by W1:W0. If N = 4, the read operation is in streaming mode, continuing until CS is raised. Streaming mode does not skip over reserved or blank registers. The readback data is valid on the falling edge of SCLK.
Rev. 0 | Page 49 of 80
AD9520-5
The default mode of the AD9520 serial control port is the bidirectional mode. In bidirectional mode, both the sent data and the readback data appear on the SDIO pin. It is also possible to set the AD9520 to unidirectional mode (0x000[7] = 1 and 0x000[0] = 1). In unidirectional mode, the readback data appears on the SDO pin. A readback request reads the data that is in the serial control port buffer area or the data that is in the active registers (see Figure 50). Readback of the buffer or active registers is controlled by 0x004[0]. The AD9520 uses Register Address 0x000 to Register Address 0xB03.
BUFFER REGISTERS ACTIVE REGISTERS
SPI MSB/LSB FIRST TRANSFERS
The AD9520 instruction word and byte data can be MSB first or LSB first. Any data written to 0x000 must be mirrored; the upper four bits ([7:4]) must mirror the lower four bits ([3:0]). This makes it irrelevant whether LSB first or MSB first is in effect. As an example of this mirroring, see the default setting for 0x000, which mirrors Bit 4 and Bit 3. This sets the long instruction mode, which is the default and the only mode supported. The default for the AD9520 is MSB first. When LSB first is set by 0x000[1] and 0x000[6], it takes effect immediately because it only affects the operation of the serial control port and does not require that an update be executed. When MSB first mode is active, the instruction and data bytes must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes must follow in order from the high address to the low address. In MSB first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. When LSB first is active, the instruction and data bytes must be written from LSB to MSB. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. In a multibyte transfer cycle, the internal byte address generator of the serial port increments for each byte. The AD9520 serial control port register address decrements from the register address just written toward 0x000 for multibyte I/O operations if the MSB first mode is active (default). If the LSB first mode is active, the register address of the serial control port increments from the address just written toward 0x232 for multibyte I/O operations. Streaming mode always terminates when it reaches 0x232. Note that unused addresses are not skipped during multibyte I/O operations. Table 39. Streaming Mode (No Addresses Are Skipped)
Write Mode LSB first MSB first Address Direction Increment Decrement Stop Sequence 0x230, 0x231, 0x232, stop 0x001, 0x000, 0x232, stop
CS SCLK/SCL SDIO/SDA SDO SERIAL CONTROL PORT
UPDATE REGISTERS
WRITE REGISTER 0x232 = 0x001 TO UPDATE REGISTERS
Figure 50. Relationship Between Serial Control Port Buffer Registers and Active Registers of the AD9520
SPI INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates whether the instruction is a read or a write. The next two bits (W1:W0) indicate the length of the transfer in bytes. The final 13 bits are the address (A12:A0) at which to begin the read or write operation. For a write, the instruction word is followed by the number of bytes of data indicated by Bits[W1:W0], see Table 38. Table 38. Byte Transfer Count
W1 0 0 1 1 W0 0 1 0 1 Bytes to Transfer 1 2 3 Streaming mode
Bits[A12:A0] select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. Only Bits[A9:A0] are needed to cover the range of the 0x232 registers used by the AD9520. Bits[A12:A10] must always be 0b. For multibyte transfers, this address is the starting byte address. In MSB first mode, subsequent bytes increment the address.
07239-037
Rev. 0 | Page 50 of 80
AD9520-5
Table 40. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB I15 R/W LSB I14 W1 I13 W0 I12 A12 = 0 I11 A11 = 0 I10 A10 = 0 I9 A9 I8 A8 I7 A7 I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 I0 A0
CS SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE DON'T CARE
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N - 1) DATA
Figure 51. Serial Control Port Write--MSB First, 16-Bit Instruction, Two Bytes of Data
CS SCLK DON'T CARE SDIO
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N - 1) DATA
REGISTER (N - 2) DATA
REGISTER (N - 3) DATA
DON'T CARE
Figure 52. Serial Control Port Read--MSB First, 16-Bit Instruction, Four Bytes of Data
tDS tS
CS
tHIGH tDH tCLK tLOW
DON'T CARE
tC
SCLK
DON'T CARE
SDIO
Figure 53. Serial Control Port Write--MSB First, 16-Bit Instruction, Timing Measurements
CS
SCLK
07239-041
tDV
SDIO SDO DATA BIT N DATA BIT N - 1
Figure 54. Timing Diagram for Serial Control Port Register Read
CS SCLK DON'T CARE SDIO DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE DON'T CARE
07239-042
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N + 1) DATA
Figure 55. Serial Control Port Write--LSB First, 16-Bit Instruction, Two Bytes of Data
Rev. 0 | Page 51 of 80
07239-040
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
07239-039
SDO DON'T CARE
07239-038
AD9520-5
tS
CS
tC
tCLK tHIGH
SCLK
tLOW
tDS
tDH
SDIO BIT N BIT N + 1
Figure 56. Serial Control Port Timing--Write
Table 41. Serial Control Port Timing
Parameter tDS tDH tCLK tS tC tHIGH tLOW tDV Description Setup time between data and rising edge of SCLK Hold time between data and rising edge of SCLK Period of the clock Setup time between the CS falling edge and SCLK rising edge (start of communication cycle) Setup time between SCLK rising edge and the CS rising edge (end of communication cycle) Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state SCLK to valid SDIO and SDO (see Figure 54)
Rev. 0 | Page 52 of 80
07239-043
AD9520-5 EEPROM OPERATIONS
The AD9520 contains an internal EEPROM (nonvolatile memory). The EEPROM can be programmed by users to create and store a user-defined register setting file when the power is off. This setting file can be used for power-up and chip reset as a default setting. The EEPROM size is 512 bytes. During the data transfer process, the write and read registers via the serial port are generally not available except for one readback register, STATUS_EEPROM. To determine the data transfer state through the serial port in SPI mode, users can read the value of STATUS_EEPROM (1 = in process and 0 = completed). In I2C mode, the user can address the AD9520 slave port with the external I2C master (send an address byte to the AD9520). If the AD9520 responds with a no acknowledge bit, the data transfer process is not done. If the AD9520 responds with an acknowledge bit, the data transfer process is completed. The user can monitor the STATUS_EEPROM register or program the STATUS pin to monitor the status of the data transfer. The user can access STATUS_EEPROM through the STATUS pin when the STATUS pin is programmed to monitor STATUS_EEPROM. Alternatively, the user can monitor the STATUS_EEPROM bit. 6. After the data transfer process is done (0xB00[0] = 0), set the enable EEPROM write register (0xB02[0]) to 0 to disable writing to the EEPROM.
To verify that the data transfer has completed correctly, the user can verify that 0xB01[0] = 0. A value of 1 in this register indicates a data transfer error.
READING FROM THE EEPROM
The following reset-related events can start the process of restoring the settings stored in EEPROM to control registers. When the EEPROM pin is set high, do any of the following: 1. 2. 3. Power-up the AD9520. Perform a hardware chip reset by pulling the RESET pin low, and then releasing RESET. Set the self-clearing soft reset bit (0x000[5]) to 1.
WRITING TO THE EEPROM
The EEPROM cannot be programmed directly through the serial port interface. To program the EEPROM and store a register setting file, do the following: 1. 2. Program the AD9520 registers to the desired circuit state. Program the EEPROM buffer registers, if necessary (see the Programming the EEPROM Buffer Segment section). This is only necessary if users want to use the EEPROM to control the default setting of some (but not all) of the AD9520 registers, or if they want to control the register setting update sequence during power-up or chip reset. 3. 4. 5. Set the enable EEPROM write bit (0xB02[0]) to 1 to enable the EEPROM. Set the REG2EEPROM bit (0xB03[0]) to 1. Set the IO_UPDATE bit (0x232[0]) to 1, which starts the process of writing data into the EEPROM to create the EEPROM setting file. This enables the AD9520 EEPROM controller to transfer the current register values, as well as the memory address and instruction bytes from the EEPROM buffer segment, into the EEPROM. After the write process is completed, the internal controller sets 0xB03[0] (REG2EEPROM) back to 0. The readback register STATUS_EEPROM (0xB00[0]) is used to indicate the data transfer status between the EEPROM and the control registers (0 = done/inactive; 1 = in process/ active). At the beginning of the data transfer, STATUS_EEPROM is set to 1 by the EEPROM controller and cleared to 0 at the end of the data transfer.
When the EEPROM pin is set low, set the self-clearing Soft_EEPROM bit (0xB02[1]) to 1. The AD9520 then starts to read the EEPROM and loads the values into the AD9520. If the EEPROM pin is low during reset or power-up, the EEPROM is not active, and the AD9520 default values are loaded instead. To verify that the data transfer has completed correctly, the user can verify that 0xB01[0] = 0. A value of 1 in this register indicates a data transfer error.
PROGRAMMING THE EEPROM BUFFER SEGMENT
The EEPROM buffer segment is a register space on the AD9520 that allows the user to specify which groups of registers are stored to the EEPROM during EEPROM programming. Normally, this segment does not need to be programmed by the user. Instead, the default power-up values for the EEPROM buffer segment allow the user to store all of the AD9520 register values from Register 0x000 to Register 0x231 to the EEPROM. For example, if users want to load only the output driver settings from the EEPROM without disturbing the PLL register settings currently stored in the AD9520, they can alter the EEPROM buffer segment to include only the registers that apply to the output drivers and exclude the registers that apply to the PLL configuration. There are two parts to the EEPROM buffer segment: register section definition groups and operational codes. Each register section definition group contains the starting address and number of bytes to be written to the EEPROM.
Rev. 0 | Page 53 of 80
AD9520-5
If the AD9520 register map were continuous from Address 0x000 to Address 0x232, only one register section definition group would consist of a starting address of 0x000 and a length of 563 bytes. However, this is not the case. The AD9520 register map is noncontiguous, and the EEPROM is only 512 bytes long. Therefore, the register section definition group tells the EEPROM controller how the AD9520 register map is segmented. There are three operational codes: IO_UPDATE, end-of-data, and pseudo-end-of-data. It is important that the EEPROM buffer segment always have either an end-of-data or a pseudo-end-of-data operational code and that an IO_UPDATE operation code appear at least once before the end-of-data op code.
End-of-Data (Operational Code 0xFF)
The EEPROM controller uses this operational code to terminate the data transfer process between EEPROM and the control register during the upload and download process. The last item appearing in the EEPROM buffer segment should be either this operational code or the pseudo-end-of-data operational code.
Pseudo-End-of-Data (Operational Code 0xFE)
The AD9520 EEPROM buffer segment has 23 bytes that can contain up to seven register section definition groups. If users want to define more than seven register section definition groups, the pseudo-end-of-data operational code can be used. During the upload process, when the EEPROM controller receives the pseudo-end-of-data operational code, it halts the data transfer process, clears the REG2EEPROM bit, and enables the AD9520 serial port. Users can then program the EEPROM buffer segment again and reinitiate the data transfer process by setting the REG2EEPROM bit (0xB03) to 1 and the IO_UPDATE register (0x232) to 1. The internal I2C master then begins writing to the EEPROM starting from the EEPROM address held from the last writing. This sequence enables more discrete instructions to be written to the EEPROM than would otherwise be possible due to the limited size of the EEPROM buffer segment. It also permits the user to write to the same register multiple times with a different value each time.
Register Section Definition Group
The register section definition group is used to define a continuous register section for the EEPROM profile. It consists of three bytes. The first byte defines how many continuous register bytes are in this group. If the user puts 0x000 in the first byte, it means there is only one byte in this group. If the user puts 0x001, it means there are two bytes in this group. The maximum number of registers in one group is 128. The next two bytes are the low byte and high byte of the memory address (16-bit) of the first register in this group.
IO_UPDATE (Operational Code 0x80)
The EEPROM controller uses this operational code to generate an IO_UPDATE signal to update the active control register bank from the buffer register bank during the download process. At a minimum, there should be at least one IO_UPDATE operational code after the end of the final register section definition group. This is needed is so that at least one IO_UPDATE occurs after all of the AD9520 registers are loaded when the EEPROM is read. If this operational code is absent during a write to the EEPROM, the register values loaded from the EEPROM are not transferred to the active register space, and these values do not take effect after they are loaded from the EEPROM to the AD9520.
Table 42. Example of EEPROM Buffer Segment
Reg Addr (Hex) Bit 7 (MSB) Start EEPROM Buffer Segment 0xA00 0 0xA01 0xA02 0xA03 0 0xA04 0xA05 0xA06 0 0xA07 0xA08 0xA09 0xA0A Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Number of bytes [6:0] of the first group of registers Address [15:8] of the first group of registers Address [7:0] of the first group of registers Number of bytes [6:0] of the second group of registers Address [15:8] of the second group of registers Address [7:0] of the second group of registers Number of bytes [6:0] of the third group of registers Address [15:8] of the third group of registers Address [7:0] of the third group of registers IO_UPDATE operational code (0x80) End-of-data operational code (0xFF)
Rev. 0 | Page 54 of 80
AD9520-5 THERMAL PERFORMANCE
Table 43. Thermal Parameters for 64-Lead LFCSP
Symbol JA JMA JMA JB JC JT Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-board characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) and JEDEC JESD51-8 Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1 Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air) Value (C/W) 22.0 19.2 17.2 11.6 1.3 0.1
The AD9520 is specified for a case temperature (TCASE). To ensure that TCASE is not exceeded, an airflow source can be used. Use the following equation to determine the junction temperature on the application PCB: TJ = TCASE + (JT x PD) where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured by the user at the top center of the package. JT is the value from Table 43. PD is the power dissipation (see the total power dissipation in Table 15.)
Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first-order approximation of TJ by the equation TJ = TA + (JA x PD) where TA is the ambient temperature (C). Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. Values of JB are provided for package comparison and PCB design considerations.
Rev. 0 | Page 55 of 80
AD9520-5 REGISTER MAP
Register addresses that are not listed in Table 44 are not used, and writing to those registers has no effect. The user should avoid writing values other than 00h to register addresses marked unused. Table 44. Register Map Overview
Addr (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Serial Port Configuration SDO active Unused Unused Soft reset LSB first/ SDO active LSB first/ Soft reset 000 Serial port addr incr (selfaddr incr (selfconfig clearing) clearing) (SPI mode) Unused Unused Unused Soft reset Unused Soft reset Serial port (self(selfconfig clearing) clearing) (IC mode) 001 Unused 002 Reserved (read-only) 003 Reserved (read-only) 004 Readback Unused Readback control active regs EEPROM ID 005 EEPROM EEPROM customer version ID (LSB) customer 006 EEPROM customer version ID (MSB) version ID 007 Unused to 00F PLL 010 PFD charge PFD polarity Charge pump current Charge pump mode PLL power-down pump 011 14-bit R counter, Bits[7:0] (LSB) R counter 012 Unused 14-bit R counter, Bits[13:8] (MSB) 013 A counter Unused 6-bit A counter 014 13-bit B counter, Bits[7:0] (LSB) B counter 015 Unused 13-bit B counter, Bits[12:8] (MSB) 016 PLL_CTRL_1 Set CP pin Reset Reset Reset all B counter Prescaler P to VCP/2 R counter A and B counters bypass counters 017 PLL_CTRL_2 STATUS pin control Antibacklash pulse width 018 PLL_CTRL_3 Enable CMOS reference input dc offset R, A, B counters SYNC pin reset Enable STATUS pin divider Enable CLK frequency monitor Lock detect counter Disable Digital digital lock lock detect detect window R path delay LD pin control Unused Default Value (Hex) 00
00
N/A N/A N/A 00
00 00 00
7D 01 00 00 03 00 06
00 06
019 01A
PLL_CTRL_4 PLL_CTRL_5
N path delay
00 00
01B
PLL_CTRL_6
01C
PLL_CTRL_7
Disable switchover deglitch Enable Status_EEPROM at STATUS pin
Ref freq monitor threshold Enable REF2 (REFIN) frequency monitor Select REF2
Enable REF1 (REFIN) frequency monitor Use REF_SEL pin Enable clock doubler Enable automatic reference switchover Disable PLL status register Stay on REF2
REFMON pin control
00
Enable REF2
Enable REF1
Enable differential reference Enable holdover
00
01D
PLL_CTRL_8
Enable XTAL OSC
Enable LD pin comparator
Unused
Enable external holdover
80
Rev. 0 | Page 56 of 80
AD9520-5
Addr (Hex) 01E 01F Parameter PLL_CTRL_9 PLL_Readback (read-only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Unused REF2 selected Bit 3 Bit 2 Bit 1 Enable zero delay REF1 freq > threshold Bit 0 (LSB) Unused Digital lock detect Default Value (Hex) 00 N/A
Unused
Holdover active
CLK freq > threshold
REF2 freq > threshold
Output Driver Control 0F0 OUT0 control
OUT0 format
OUT0 CMOS configuration OUT1 CMOS configuration OUT2 CMOS configuration OUT3 CMOS configuration OUT4 CMOS configuration OUT5 CMOS configuration OUT6 CMOS configuration OUT7 CMOS configuration OUT8 CMOS configuration OUT9 CMOS configuration OUT10 CMOS configuration OUT11 CMOS configuration CSDLD En CSDLD En OUT6 OUT5 Unused
OUT0 polarity
OUT0 LVPECL differential voltage OUT1 LVPECL differential voltage OUT2 LVPECL differential voltage OUT3 LVPECL differential voltage OUT4 LVPECL differential voltage OUT5 LVPECL differential voltage OUT6 LVPECL differential voltage OUT7 LVPECL differential voltage OUT8 LVPECL differential voltage OUT9 LVPECL differential voltage OUT10 LVPECL differential voltage OUT11 LVPECL differential voltage CSDLD En OUT2 CSDLD En OUT10 CSDLD En OUT1 CSDLD En OUT9
0F1
OUT1 control
OUT1 format
OUT1 polarity
0F2
OUT2 control
OUT2 format
OUT2 polarity
0F3
OUT3 control
OUT3 format
OUT3 polarity
0F4
OUT4 control
OUT4 format
OUT4 polarity
0F5
OUT5 control
OUT5 format
OUT5 polarity
0F6
OUT6 control
OUT6 format
OUT6 polarity
0F7
OUT7 control
OUT7 format
OUT7 polarity
0F8
OUT8 control
OUT8 format
OUT8 polarity
0F9
OUT9 control
OUT9 format
OUT9 polarity
0FA
OUT10 control
OUT10 format
OUT10 polarity
0FB
OUT11 control
OUT11 format
OUT11 polarity
0FC 0FD
Enable output on CSDLD Enable output on CSDLD
CSDLD En OUT7
CSDLD En OUT4
0FE to 18F LVPECL Channel Dividers 190 Divider 0 (PECL) 191 Divider 0 bypass 192
CSDLD En OUT3 CSDLD En OUT11 Unused
OUT0 LVPECL power-down OUT1 LVPECL power-down OUT2 LVPECL power-down OUT3 LVPECL power-down OUT4 LVPECL power-down OUT5 LVPECL power-down OUT6 LVPECL power-down OUT7 LVPECL power-down OUT8 LVPECL power-down OUT9 LVPECL power-down OUT10 LVPECL power-down OUT11 LVPECL power-down CSDLD En OUT0 CSDLD En OUT8
64
64
64
64
64
64
64
64
64
64
64
64
00 00 00
Divider 0 low cycles Divider 0 Divider 0 ignore force SYNC high Unused
Divider 0 start high
Divider 0 high cycles Divider 0 phase offset Channel 0 powerdown Channel 0 direct-tooutput Disable Divider 0 DCC
77 00
00
Rev. 0 | Page 57 of 80
AD9520-5
Addr (Hex) 193 194 Parameter Divider 1 (PECL) Bit 7 (MSB) Divider 1 bypass Bit 6 Bit 5 Divider 1 low cycles Divider 1 Divider 1 force ignore SYNC high Unused Bit 4 Divider 1 start high Unused Bit 3 Bit 2 Bit 1 Divider 1 high cycles Divider 1 phase offset Channel 1 Channel 1 direct-topowerdown output Divider 2 high cycles Divider 2 phase offset Channel 2 Channel 2 powerdirect-todown output Divider 3 high cycles Divider 3 phase offset Channel 3 powerdown Channel 3 direct-tooutput Bit 0 (LSB) Default Value (Hex) 33 00
195
Disable Divider 1 DCC
00
196 197
Divider 2 (PECL)
Divider 2 bypass
198
Divider 2 low cycles Divider 2 Divider 2 ignore force SYNC high Unused
Divider 2 start high Unused
11 00
Disable Divider 2 DCC
00
199 19A
Divider 3 (PECL)
Divider 3 bypass
19B
Divider 3 low cycles Divider 3 Divider 3 force ignore high SYNC Unused
Divider 3 start high Unused
00 00
Disable Divider 3 DCC
00
19C to 1DF VCO Divider and CLK Input 1E0 VCO divider 1E1 Input CLKs Unused
Unused
00
Unused Unused (default = 01b) Power down clock input section
Unused Reserved
VCO divider Bypass VCO divider
00 20
1E2 to 22A System 230 Power-down and SYNC
Unused
00
Unused
Disable power-on SYNC
Powerdown SYNC
231 Update All Registers 232 IO_UPDATE 233 to 9FF EEPROM Buffer Segment A00 EEPROM Buffer Segment Register 1 A01 EEPROM Buffer Segment Register 2 A02 EEPROM Buffer Segment Register 3 A03 EEPROM Buffer Segment Register 4
Unused Unused Unused
Powerdown distribution reference Unused
Soft SYNC
00
00 IO_UPDATE (self-clearing) 00 00
0
EEPROM Buffer Segment Register 1 (default: number of bytes for Group 1)
00
EEPROM Buffer Segment Register 2 (default: Bits[15:8] of starting register address for Group 1)
00
EEPROM Buffer Segment Register 3 (default: Bits[7:0] of starting register address for Group 1)
00
0
EEPROM Buffer Segment Register 4 (default: number of bytes for Group 2)
02
Rev. 0 | Page 58 of 80
AD9520-5
Addr (Hex) A04 Parameter EEPROM Buffer Segment Register 5 EEPROM Buffer Segment Register 6 EEPROM Buffer Segment Register 7 EEPROM Buffer Segment Register 8 EEPROM Buffer Segment Register 9 EEPROM Buffer Segment Register 10 EEPROM Buffer Segment Register 11 EEPROM Buffer Segment Register 12 EEPROM Buffer Segment Register 13 EEPROM Buffer Segment Register 14 EEPROM Buffer Segment Register 15 EEPROM Buffer Segment Register 16 EEPROM Buffer Segment Register 17 EEPROM Buffer Segment Register 18 EEPROM Buffer Segment Register 19 EEPROM Buffer Segment Register 20 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) EEPROM Buffer Segment Register 5 (default: Bits[15:8] of starting register address for Group 2) Default Value (Hex) 00
A05
EEPROM Buffer Segment Register 6 (default: Bits[7:0] of starting register address for Group 2)
04
A06
0
EEPROM Buffer Segment Register 7 (default: number of bytes for Group 3)
0E
A07
EEPROM Buffer Segment Register 8 (default: Bits[15:8] of starting register address for Group 3)
00
A08
EEPROM Buffer Segment Register 9 (default: Bits[7:0] of starting register address for Group 3)
10
A09
0
EEPROM Buffer Segment Register 10 (default: number of bytes for Group 4)
0E
A0A
EEPROM Buffer Segment Register 11 (default: Bits[15:8] of starting register address for Group 4)
00
A0B
EEPROM Buffer Segment Register 12 (default: Bits[7:0] of starting register address for Group 4)
F0
A0C
0
EEPROM Buffer Segment Register 13 (default: number of bytes for Group 5)
0B
A0D
EEPROM Buffer Segment Register 14 (default: Bits[15:8] of starting register address for Group 5)
01
A0E
EEPROM Buffer Segment Register 15 (default: Bits[7:0] of starting register address for Group 5)
90
A0F
0
EEPROM Buffer Segment Register 16 (default: number of bytes for Group 6)
01
A10
EEPROM Buffer Segment Register 17 (default: Bits[15:8] of starting register address for Group 6)
01
A11
EEPROM Buffer Segment Register 18 (default: Bits[7:0] of starting register address for Group 6)
E0
A12
0
EEPROM Buffer Segment Register 19 (default: number of bytes for Group 7)
01
A13
EEPROM Buffer Segment Register 20 (default: Bits[15:8] of starting register address for Group 7)
02
Rev. 0 | Page 59 of 80
AD9520-5
Addr (Hex) A14 Parameter EEPROM Buffer Segment Register 21 EEPROM Buffer Segment Register 22 EEPROM Buffer Segment Register 23 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) EEPROM Buffer Segment Register 21 (default: Bits[7:0] of starting register address for Group 7) Default Value (Hex) 30
A15
EEPROM Buffer Segment Register 22 (default: IO_UPDATE from EEPROM)
80
A16
EEPROM Buffer Segment Register 23 (default: end of data)
FF
A17 to AFF EEPROM Control B00 EEPROM status (read-only) B01 EEPROM error checking (read-only) B02 EEPROM Control 1 B03 EEPROM Control 2
Unused
00
Unused
Unused
STATUS_ EEPROM EEPROM data error Enable EEPROM write REG2EEPROM (self-clearing)
00
Unused
Unused
00
Unused
Soft_EEPROM (self-clearing) Unused
00
Unused
00
Rev. 0 | Page 60 of 80
AD9520-5 REGISTER MAP DESCRIPTIONS
Table 45 through Table 55 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Reference to a specific bit or range of bits within a register is indicated by squared brackets. For example, [3] refers to Bit 3 and [5:2] refers to the range of bits from Bit 5 through Bit 2. Table 45. SPI Mode Serial Port Configuration
Reg Addr (Hex) 000 Bit(s) [7] Name SDO active Description Selects unidirectional or bidirectional data transfer mode. [7] = 0; SDIO pin used for write and read; SDO is high impedance (default). [7] = 1; SDO used for read; SDIO used for write; unidirectional mode. SPI MSB or LSB data orientation. (This register is ignored in I2C mode.) [6] = 0; data-oriented MSB first; addressing decrements (default). [6] = 1; data-oriented LSB first; addressing increments. Soft reset. [5] = 1 (self-clearing). Soft reset; restores default values to internal registers. Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is in MSB or LSB first mode (see Register 0x000[6]). Set bits as follows: [0] = [7] [1] = [6] [2] = [5] [3] = [4] Select register bank used for a readback. [0] = 0; read back buffer registers (default). [0] = 1; read back active registers.
000
[6]
LSB first/addr incr
000 000 000
[5] [4] [3:0]
Soft reset Unused Mirror[7:4]
004
[0]
Readback active registers
Table 46. I2C Mode Serial Port Configuration
Reg Addr (Hex) 000 000 000 000 Bit(s) [7:6] [5] [4] [3:0] Name Unused Soft reset Unused Mirror[7:4] Description Soft reset. [5] = 1 (self-clearing). Soft reset; restores default values to internal registers. Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is in MSB or LSB first mode (see Register 0x000[6]). Set bits as follows: [0] = [7] [1] = [6] [2] = [5] [3] = [4] Select register bank used for a readback. [0] = 0; read back buffer registers (default). [0] = 1; read back active registers.
004
[0]
Readback active registers
Table 47. EEPROM ID
Reg Addr (Hex) 005 Bit(s) [7:0] Name EEPROM customer version ID (LSB) EEPROM customer version ID (MSB) Description 16-bit EEPROM ID[7:0]. This register, along with 0x006, allows the user to store a unique ID to identify which version of the AD9520 register settings is stored in the EEPROM. It does not affect AD9520 operation in any way (default: 0x00). 16-bit EEPROM ID[15:8]. This register, along with 0x005, allows the user to store a unique ID to identify which version of the AD9520 register settings is stored in the EEPROM. It does not affect AD9520 operation in any way (default: 0x00).
006
[7:0]
Rev. 0 | Page 61 of 80
AD9520-5
Table 48. PLL
Reg. Addr (Hex) Bit(s) Name 010 [7] PFD polarity
010
[6:4] CP current
010
[3:2] CP mode
Description Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO. [7] = 0; positive (higher control voltage produces higher frequency) (default). [7] = 1; negative (higher control voltage produces lower frequency). Charge pump current (with CPRSET = 5.1 k). [6] [5] [4] ICP (mA) 0 0 0 0.6 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 (default) Charge pump operating mode.
010
011 012 013 014 015 016
[3] [2] Charge Pump Mode 0 0 High impedance state. 0 1 Force source current (pump-up). 1 0 Force sink current (pump-down). 1 1 Normal operation (default). [1:0] PLL powerPLL operating mode. down [1] [0] Mode 0 0 Normal operation; this mode must be selected to use the PLL. 0 1 Asynchronous power-down (default). 1 0 Unused. 1 1 Synchronous power-down. [7:0] 14-bit R counter, Reference divider LSBs--lower eight bits. The reference divider (also called the R divider or R counter) is Bits[7:0] (LSB) 14 bits long. The lower eight bits are in this register (default: 0x01). [5:0] 14-bit R counter, Reference divider MSBs--upper six bits. The reference divider (also called the R divider or R counter) is Bits[13:8] (MSB) 14 bits long. The upper six bits are in this register (default: 0x00). [5:0] 6-bit A counter A counter (part of N divider). The N divider is also called the feedback divider (default: 0x00). [7:0] 13-bit B counter, Bits[7:0] (LSB) [4:0] 13-bit B counter, Bits[12:8] (MSB) [7] Set CP pin to VCP/2 [6] B counter (part of N divider)--lower eight bits. The N divider is also called the feedback divider (default: 0x03). B counter (part of N divider)--upper five bits. The N divider is also called the feedback divider (default: 0x00).
016
016
[5]
016
[4]
Sets the CP pin to one-half of the VCP supply voltage. [7] = 0; CP normal operation (default). [7] = 1; CP pin set to VCP/2. Reset R counter Reset R counter (R divider). [6] = 0; normal (default). [6] = 1; hold R counter in reset. Reset A and B counters (part of N divider). Reset A and B counters [5] = 0; normal (default). [5] = 1; hold A and B counters in reset. Reset R, A, and B counters. Reset all counters [4] = 0; normal (default). [4] = 1; hold R, A, and B counters in reset.
Rev. 0 | Page 62 of 80
AD9520-5
Reg. Addr (Hex) Bit(s) Name 016 [3] B counter bypass Description B counter bypass. This is only valid when operating the prescaler in FD mode. [3] = 0; normal (default). [3] = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider. Prescaler: DM = dual modulus and FD = fixed divide. The Prescaler P is part of the feedback divider. [2] [1] [0] Mode Prescaler 0 0 0 FD Divide-by-1. 0 0 1 FD Divide-by-2. 0 1 0 DM Divide-by-2 and divide-by-3 when A 0; divide-by-2 when A = 0. 0 1 1 DM Divide-by-4 and divide-by-5 when A 0; divide-by-4 when A = 0. 1 0 0 DM Divide-by-8 and divide-by-9 when A 0; divide-by-8 when A = 0. 1 0 1 DM Divide-by-16 and divide-by-17 when A 0; divide-by-16 when A = 0. 1 1 0 DM Divide-by-32 and divide-by-33 when A 0; divide-by-32 when A = 0 (default). 1 1 1 FD Divide-by-3. Selects the signal that appears at the STATUS pin. 0x01D[7] must be 0 to reprogram the STATUS pin. Level or Dynamic [7] [6] [5] [4] [3] [2] Signal Signal at STATUS Pin 0 0 0 0 0 0 LVL Ground, dc (default). 0 0 0 0 0 1 DYN N divider output (after the delay). 0 0 0 0 1 0 DYN R divider output (after the delay). 0 0 0 0 1 1 DYN A divider output. 0 0 0 1 0 0 DYN Prescaler output. 0 0 0 1 0 1 DYN PFD up pulse. 0 0 0 1 1 0 DYN PFD down pulse. 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified. The selections that follow are the same as for REFMON. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status REF1 frequency (active high). 1 0 1 0 0 0 LVL Status REF2 frequency (active high). 1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of CLK frequency (active high). 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL DLD; active high. 1 0 1 1 1 0 LVL Holdover active (active high). 1 0 1 1 1 1 LVL LD pin comparator output (active high). 1 1 0 0 0 0 LVL VS (PLL power supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode).
Rev. 0 | Page 63 of 80
016
[2:0] Prescaler P
017
[7:2] STATUS pin control
AD9520-5
Reg. Addr (Hex) Bit(s) Name Description Level or Dynamic [2] Signal 0 DYN 1 0 LVL LVL
[7] 1 1 1
[6] [5] 1 0 1 1 0 0
[4] 1 1 1
[3] 0 0 1
017
[1:0] Antibacklash pulse width
018
[7]
Enable CMOS reference input dc offset
018
[6:5] Lock detect counter
018
[4]
Digital lock detect window
018
[3]
Disable digital lock detect
019
[7:6] R, A, B counters SYNC pin reset
1 1 0 1 1 1 LVL 1 1 1 0 0 0 LVL 1 1 1 0 0 1 LVL 1 1 1 0 1 0 LVL 1 1 1 0 1 1 LVL 1 1 1 1 0 0 LVL 1 1 1 1 0 1 LVL 1 1 1 1 1 0 LVL 1 1 1 1 1 1 LVL [1] [0] Antibacklash Pulse Width (ns) 0 0 2.9 (default) 0 1 1.3 1 0 6.0 1 1 2.9 Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost. [7] = 0; disable dc offset (default). [7] = 1; enable dc offset. Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked condition. [6] [5] PFD Cycles to Determine Lock 0 0 5 (default) 0 1 16 1 0 64 1 1 255 If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold. [4] = 0; high range (default). [4] = 1; low range. Digital lock detect operation. [3] = 0; normal lock detect operation (default). [3] = 1; disable lock detect. [7] [6] Action 0 0 Do nothing on SYNC (default). 0 1 1 1 0 1 Asynchronous reset. Synchronous reset. Do nothing on SYNC.
Signal at STATUS Pin Unselected reference to PLL (not available when in differential mode). Status of selected reference (status of differential reference); active low. Status of unselected reference (not available in differential mode); active low. Status of REF1 frequency (active low). Status of REF2 frequency (active low). (Status of REF1 frequency) AND (status of REF2 frequency). (DLD) AND (Status of selected reference) AND (status of VCO). Status of CLK frequency (active low). Selected reference (low = REF2, high = REF1). DLD (active low). Holdover active (active low). LD pin comparator output (active low).
019 019
[5:3] R path delay [2:0] N path delay
R path delay, see Table 2 (default: 0x0). N path delay, see Table 2 (default: 0x0).
Rev. 0 | Page 64 of 80
AD9520-5
Reg. Addr (Hex) Bit(s) Name 01A [7] Enable STATUS pin divider Description Enables a divide-by-4 on the STATUS pin. This makes it easier to look at low duty-cycle signals out of the R and N dividers. [7] = 0; divide-by-4 disabled on STATUS pin (default). [7] = 1; divide-by-4 enabled on STATUS pin. [6] Ref freq monitor Sets the reference (REF1/REF2) frequency monitor's detection threshold frequency. This does not affect the CLK threshold frequency monitor's detection threshold (see Table 14, REF1, REF2, and CLK frequency status monitor parameter). [6] = 0; frequency valid if frequency is above 1.02 MHz (default). [6] = 1; frequency valid if frequency is above 6 kHz. [5:0] LD pin Selects the signal that is connected to the LD pin. control Level or Dynamic [5] [4] [3] [2] [1] [0] Signal Signal at LD Pin 0 0 0 0 0 0 LVL Digital lock detect (high = lock; low = unlock, default). 0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 1 HIZ Tristate (high-Z) LD pin. 0 0 0 1 0 0 CUR Current source lock detect (110 A when DLD is true). 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified. The selections that follow are the same as for REFMON. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status REF1 frequency (active high). 1 0 1 0 0 0 LVL Status REF2 frequency (active high). 1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of CLK frequency (active high). 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL DLD; active high. 1 0 1 1 1 0 LVL Holdover active (active high). 1 0 1 1 1 1 LVL N/A, do not use. 1 1 0 0 0 0 LVL VS (PLL supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency).
Rev. 0 | Page 65 of 80
01A
01A
AD9520-5
Reg. Addr (Hex) Bit(s) Name Description Level or Dynamic [5] [4] [3] [2] [1] [0] Signal Signal at LD Pin 1 1 1 0 1 0 LVL (DLD) AND (Status of selected reference) AND (status of VCO). 1 1 1 0 1 1 LVL Status of CLK frequency (active low). 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 1 0 1 LVL DLD; active low. 1 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 1 LVL N/A, do not use. Enables or disables the external CLK frequency monitor. [7] = 0; disable the external CLK frequency monitor (default). [7] = 1; enable the external CLK frequency monitor. Enables or disables the REF2 frequency monitor. [6] = 0; disable the REF2 frequency monitor (default). [6] = 1; enable the REF2 frequency monitor. REF1 (REFIN) frequency monitor enabled; this is for both REF1 (single-ended) and REFIN (differential) inputs (as selected by differential reference mode). [5] = 0; disable the REF1 (REFIN) frequency monitor (default). [5] = 1; enable the REF1 (REFIN) frequency monitor. Selects the signal that is connected to the REFMON pin. Level or Dynamic [4] [3] [2] [1] [0] Signal Signal at REFMON Pin 0 0 0 0 0 LVL Ground, dc (default). 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 0 0 1 1 1 LVL Status REF1 frequency (active high). 0 1 0 0 0 LVL Status REF2 frequency (active high). 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 0 1 0 1 1 LVL Status of CLK frequency (active high). 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 0 1 1 0 1 LVL DLD; active low. 0 1 1 1 0 LVL Holdover active (active high). 0 1 1 1 1 LVL LD pin comparator output (active high). 1 0 0 0 0 LVL VS (PLL supply). 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode).
01B
[7]
Enable CLK frequency monitor Enable REF2 (REFIN) frequency monitor Enable REF1 (REFIN) frequency monitor
01B
[6]
01B
[5]
01B
[4:0] REFMON pin control
Rev. 0 | Page 66 of 80
AD9520-5
Reg. Addr (Hex) Bit(s) Name Description Level or Dynamic [0] Signal 1 LVL
01C
[7]
01C
[6]
01C
[5]
01C
[4]
01C
[3]
01C
[2]
01C
[1]
01C
[0]
01D
[7]
01D
[6]
Signal at REFMON Pin Status of selected reference (status of differential reference); active low. 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 1 0 1 1 LVL Status of CLK frequency (active low). 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 0 1 LVL DLD; active low. 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 LVL LD pin comparator output (active low). Disables or enables the switchover deglitch circuit. Disable switchover [7] = 0; enable the switchover deglitch circuit (default). deglitch [7] = 1; disable the switchover deglitch circuit. Select REF2 If Register 0x01C[5] = 0, selects the reference for PLL when in manual; register selected reference control. [6] = 0; select REF1 (default). [6] = 1; select REF2. If Register 0x01C[4] = 0 (manual), sets the method of PLL reference selection. Use REF_SEL pin [5] = 0; use Register 0x01C[6] (default). [5] = 1; use REF_SEL pin. Enable Automatic or manual reference switchover. Single-ended reference mode must be selected by automatic Register 0x01C[0] = 0. reference [4] = 0; manual reference switchover (default). switchover [4] = 1; automatic reference switchover. Setting this bit also powers on REF1 and REF2 and overrides the settings in Register 0x01C[2:1]. Stay on REF2 Stays on REF2 after switchover. [3] = 0; return to REF1 automatically when REF1 status is good again (default). [3] = 1; stay on REF2 after switchover. Do not automatically return to REF1. Enable REF2 This bit turns the REF2 power on. This bit is overridden when automatic reference switchover is enabled. [2] = 0; REF2 power off (default). [2] = 1; REF2 power on. Enable REF1 This bit turns the REF1 power on. This bit is overridden when automatic reference switchover is enabled. [1] = 0; REF1 power off (default). [1] = 1; REF1 power on. Enable Selects the PLL reference mode, differential or single-ended. differential Register 0x01C[2:1] should be cleared when this bit is set. reference [0] = 0; single-ended reference mode (default). [0] = 1; differential reference mode. Enables the Status_EEPROM signal at the STATUS pin. Enable Status_EEPROM [7] = 0; the STATUS pin is controlled by the 0x017[7:2] selection. at STATUS pin [7] = 1; select the Status_EEPROM signal at the STATUS pin. This bit overrides 0x017[7:2] (default). Enables the maintaining amplifier needed by a crystal oscillator at the PLL reference input. Enable XTAL OSC [6] = 0; crystal oscillator maintaining amplifier disabled (default). [6] = 1; crystal oscillator maintaining amplifier enabled.
[4] 1
[3] 0
[2] 1
[1] 0
Rev. 0 | Page 67 of 80
AD9520-5
Reg. Addr (Hex) Bit(s) Name 01D [5] Enable clock doubler 01D [4] Description Enable PLL reference input clock doubler. [5] = 0; doubler disabled (default). [5] = 1; doubler enabled. Disables the PLL status register readback. Disable PLL status register [4] = 0; PLL status register enabled (default). [4] = 1; PLL status register disabled. If this bit is set, Register 01F is not automatically updated. Enable LD pin Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode. comparator When the AD9520 is in internal (automatic) holdover mode, this enables the use of the voltage on the LD pin to determine if the PLL was previously in a locked state (see Figure 34). Otherwise, this can be used with the REFMON and STATUS pins to monitor the voltage on the LD pin. [3] = 0; disable LD pin comparator and ignore the LD pin voltage; internal/automatic holdover controller treats this pin as true (high, default). [3] = 1; enable LD pin comparator (use LD pin voltage to determine if the PLL was previously locked). Enable external Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.) holdover [1] = 0; automatic holdover mode, holdover controlled by automatic holdover circuit (default). [1] = 1; external holdover mode, holdover controlled by SYNC pin. 01D [0] Enables the internally controlled holdover function. [0] = 0; holdover disabled (default). [0] = 1; holdover enabled. Enables zero delay function. Enable zero delay [1] = 0; disables zero delay function (default). [1] = 1; enables zero delay function. Holdover active Readback register. Indicates if the part is in the holdover state (see Figure 34). This is not the same as (read-only) holdover enabled. [5] = 0; not in holdover. [5] = 1; holdover state active. Readback register. Indicates which PLL reference is selected as the input to the PLL. REF2 selected (read-only) [4] = 0; REF1 selected (or differential reference if in differential mode). [4] = 1; REF2 selected. CLK frequency Readback register. Indicates if the external CLK input frequency is greater than the threshold (see Table 14, > threshold REF1, REF2, and external CLK frequency status monitor parameter). (read-only) [3] = 0; the external CLK frequency is less than the threshold. [3] = 1; the external CLK frequency is greater than the threshold. REF2 frequency Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency > threshold set by Register 0x01A[6]. (read-only) [2] = 0; REF2 frequency is less than the threshold frequency. [2] = 1; REF2 frequency is greater than the threshold frequency. REF1 frequency Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency > threshold set by Register 0x01A[6]. (read-only) [1] = 0; REF1 frequency is less than the threshold frequency. [1] = 1; REF1 frequency is greater than the threshold frequency. Readback register. Digital lock detect. Digital lock detect [0] = 0; PLL is not locked. (read-only) [0] = 1; PLL is locked. Enable holdover
01D
[3]
01D
[1]
01E
[1]
01F
[5]
01F
[4]
01F
[3]
01F
[2]
01F
[1]
01F
[0]
Rev. 0 | Page 68 of 80
AD9520-5
Table 49. Output Driver Control
Reg. Addr (Hex) Bit(s) Name 0F0 [7] OUT0 format
0F0
[6:5]
0F0
[4:3]
0F0
[2:1]
0F0
[0]
0F1 0F2 0F3 0F4 0F5 0F6 0F7 0F8 0F9 0FA 0FB 0FC
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7]
Description Selects the output type for OUT0. [7] = 0; LVPECL (default). [7] = 1; CMOS. Sets the CMOS output configuration for OUT0 when 0x0F0[7] = 1. OUT0 CMOS configuration [6:5] OUT0A OUT0B 00 Tristate Tristate 01 On Tristate 10 Tristate On 11 (default) On On OUT0 polarity Sets the output polarity for OUT0. [7] [4] [3] Output Type OUT0A OUT0B 0 (default) X 0 (default) LVPECL Noninverting Inverting 0 X 1 LVPECL Inverting Noninverting 1 0 (default) 0 CMOS Noninverting Noninverting 1 0 1 CMOS Inverting Inverting 1 1 0 CMOS Noninverting Inverting 1 1 1 CMOS Inverting Noninverting OUT0 LVPECL Sets the LVPECL output differential voltage (VOD). differential [2] [1] VOD (mV) voltage 0 0 400 0 1 600 1 (default) 0 (default) 780 1 1 960 OUT0 LVPECL LVPECL power-down. power-down [0] = 0; normal operation (default). [0] = 1; safe power-down. OUT1 control This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0. OUT2 control This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0. OUT3 control This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0. OUT4 control This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0. OUT5 control This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0. OUT6 control This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0. OUT7 control This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0. OUT8 control This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0. OUT9 control This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0. OUT10 control This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0. OUT11 control This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0. CSDLD En OUT7 OUT7 is enabled only if CSDLD is high. [7] CSDLD Signal OUT7 Enable Status 0 0 Not affected by CSDLD signal (default). 1 0 Asynchronous power-down. 1 1 Asynchronously enable OUT7 if not powered down by other settings. To use this feature, the user must use current source digital lock detect and set the enable LD pin comparator bit (0x01D[3]).
Rev. 0 | Page 69 of 80
AD9520-5
Reg. Addr (Hex) 0FC 0FC 0FC 0FC 0FC 0FC 0FC 0FD 0FD 0FD 0FD Bit(s) [6] [5] [4] [3] [2] [1] [0] [3] [2] [1] [0] Name CSDLD En OUT6 CSDLD En OUT5 CSDLD En OUT4 CSDLD En OUT3 CSDLD En OUT2 CSDLD En OUT1 CSDLD En OUT0 CSDLD En OUT11 CSDLD En OUT10 CSDLD En OUT9 CSDLD En OUT8 Description OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Table 50. LVPECL Channel Dividers
Reg. Addr (Hex) Bit(s) Name 190 [7:4] Divider 0 low cycles 190 191 [3:0] [7] Divider 0 high cycles Divider 0 bypass
191
[6]
Divider 0 ignore SYNC
191
[5]
Divider 0 force high
191
[4]
Divider 0 start high
191 192
[3:0] [2]
Divider 0 phase offset Channel 0 power-down
192
[1]
Channel 0 direct-to-output
192
[0]
Disable Divider 0 DCC
Description Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x7 means that the divider is high for eight input clock cycles (default: 0x7). Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. Forces divider output to high. This requires that ignore SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. Phase offset (default: 0x0). Channel 0 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 are put into safe powerdown mode by setting this bit.) Connects OUT0, OUT1, and OUT2 to Divider 0 or directly to CLK. [1] = 0; OUT0, OUT1, and OUT2 are connected to Divider 0 (default). [1] = 1; If 0x1E1[0] = 0, the CLK is routed directly to OUT0, OUT1, and OUT2. If 0x1E1[0] = 1, there is no effect. Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction.
Rev. 0 | Page 70 of 80
AD9520-5
Reg. Addr (Hex) Bit(s) Name 193 [7:4] Divider 1 low cycles 193 194 [3:0] [7] Divider 1 high cycles Divider 1 bypass Description Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x3 means that the divider is low for four input clock cycles (default: 0x3). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x3 means that the divider is high for four input clock cycles (default: 0x3). Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. Forces divider output to high. This requires that ignore SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. Phase offset (default: 0x0). Channel 1 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT3/OUT3, OUT4/OUT4, and OUT5/OUT5 are put into safe powerdown mode by setting this bit.) Connects OUT3, OUT4, and OUT5 to Divider 1 or directly to CLK. [1] = 0; OUT3, OUT4, and OUT5 are connected to Divider 1 (default). [1] = 1; If 0x1E1[0] = 0, the CLK is routed directly to OUT3, OUT4, and OUT5. If 0x1E1[0] = 1, there is no effect. Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x1 means the divider is low for two input clock cycles (default: 0x1). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x1 means the divider is high for two input clock cycles (default: 0x1). Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. Forces divider output to high. This requires that ignore SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. Phase offset(default: 0x0).
194
[6]
Divider 1 ignore SYNC
194
[5]
Divider 1 force high
194
[4]
Divider 1 start high
194 195
[3:0] [2]
Divider 1 phase offset Channel 1 power-down
195
[1]
Channel 1 direct-to-output
195
[0]
Disable Divider 1 DCC
196 196 197
[7:4] [3:0] [7]
Divider 2 low cycles Divider 2 high cycles Divider 2 bypass
197
[6]
Divider 2 ignore SYNC
197
[5]
Divider 2 force high
197
[4]
Divider 2 start high
197
[3:0]
Divider 2 phase offset
Rev. 0 | Page 71 of 80
AD9520-5
Reg. Addr (Hex) Bit(s) Name 198 [2] Channel 2 power-down Description Channel 2 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 are put into safe powerdown mode by setting this bit.) Connects OUT6, OUT7, and OUT8 to Divider 2 or directly to CLK. [1] = 0; OUT6, OUT7, and OUT8 are connected to Divider 2 (default). [1] = 1: If 0x1E1[0] = 0, the CLK is routed directly to OUT6, OUT7, and OUT8. If 0x1E1[0] = 1, there is no effect. Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default: 0x0). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default: 0x0). Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. Forces divider output to high. This requires that ignore SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. Phase offset (default: 0x0). Channel 3 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 are put into safe power-down mode by setting this bit.) Connects OUT9, OUT10, and OUT11 to Divider 3 or directly to CLK. [1] = 0; OUT9, OUT10, and OUT11 are connected to Divider 3 (default). [1] = 1: If 0x1E1[0] = 0, the CLK is routed directly to OUT9, OUT10, and OUT11. If 0x1E1[0] = 1, there is no effect. Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction.
198
[1]
Channel 2 direct-to-output
198
[0]
Disable Divider 2 DCC
199 199 19A
[7:4] [3:0] [7]
Divider 3 low cycles Divider 3 high cycles Divider 3 bypass
19A
[6]
Divider 3 ignore SYNC
19A
[5]
Divider 3 force high
19A
[4]
Divider 3 start high
19A 19B
[3:0] [2]
Divider 3 phase offset Channel 3 power-down
19B
[1]
Channel 3 direct-to-output
19B
[0]
Disable Divider 3 DCC
Rev. 0 | Page 72 of 80
AD9520-5
Table 51. VCO Divider and CLK Input
Reg. Addr (Hex) Bit(s) Name 1E0 [2:0] VCO divider
1E1
[4]
1E1
[0]
Description [2] [1] [0] Divide 0 0 0 2 (default) 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 Output static 1 1 0 1 (bypass) 1 1 1 Output static Power-down clock input section Powers down the clock input section (including the CLK buffer, VCO divider, and CLK tree). [4] = 0; normal operation (default). [4] = 1; power down. Bypass VCO divider Bypasses or uses the VCO divider. [0] = 0; use the VCO divider (default). [0] = 1; bypass the VCO divider.
Table 52. System
Reg. Addr (Hex) Bit(s) Name 230 [3] Disable power-on SYNC
230
[2]
Power-down SYNC
230
[1]
Power-down distribution reference
230
[0]
Soft SYNC
Description Power-on SYNC mode. Used to disable the antiruntpulse circuitry. [3] = 0; enable the antiruntpulse circuitry (default). [3] = 1; disable the antiruntpulse circuitry. Powers down the SYNC function. [2] = 0; normal operation of the SYNC function (default). [2] = 1; power-down SYNC circuitry. Powers down the reference for the distribution section. [1] = 0; normal operation of the reference for the distribution section (default). [1] = 1; powers down the reference for the distribution section. The soft SYNC bit works in the same way as the SYNC pin, except that the polarity of the bit is reversed; that is, a high level forces selected channels into a predetermined static state, and a 1-to-0 transition triggers a SYNC. [0] = 0; same as SYNC high. [0] = 1; same as SYNC low.
Table 53. Update All Registers
Reg. Addr (Hex) Bit(s) Name 232 [0] IO_UPDATE
Description This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0. [0] = 1 (self-clearing); update all active registers to the contents of the buffer registers.
Rev. 0 | Page 73 of 80
AD9520-5
Table 54. EEPROM Buffer Segment
Reg. Addr (Hex) Bit(s) Name A00 to [7:0] EEPROM Buffer A16 Segment Register 1 to EEPROM Buffer Segment Register 23
Description The EEPROM buffer segment section stores the starting address and number of bytes that are to be stored and read back to and from the EEPROM. Because the AD9520 register space is noncontiguous, the EEPROM controller needs to know the starting address and number of bytes in the AD9520 register space to store and retrieve from the EEPROM. In addition, there are special instructions for the EEPROM controller, operational codes (that is, IO_UPDATE and end-of-data) that are also stored in the EEPROM buffer segment. The on-chip default setting of the EEPROM buffer segment registers is designed such that all registers are transferred to/from the EEPROM, and an IO_UPDATE is issued after transfer. See the Programming the EEPROM Buffer Segment section for more information.
Table 55. EEPROM Control
Reg. Addr (Hex) Bit(s) Name Description B00 [0] STATUS_EEPROM This read-only register indicates the status of the data transferred between the EEPROM and the buffer (read-only) register bank during the writing and reading of the EEPROM. This signal is also available at the STATUS pin when 0x01D[7] is set. [0] = 0; data transfer is done. [0] = 1; data transfer is not done. B01 [0] This read-only register indicates an error during the data transferred between the EEPROM and the buffer. EEPROM data error [0] = 0; no error. Data is correct. (read-only) [0] = 1; incorrect data detected. B02 [1] Soft_EEPROM When the EEPROM pin is tied low, setting Soft_EEPROM resets the AD9520 using the settings saved in EEPROM. [1] = 1; soft reset with EEPROM settings (self-clearing). B02 [0] Enable EEPROM Enables the user to write to the EEPROM. write [0] = 0; EEPROM write protection is enabled. User cannot write to EEPROM (default). [0] = 1; EEPROM write protection is disabled. User can write to EEPROM. B03 [0] REG2EEPROM Transfers data from the buffer register to the EEPROM (self-clearing). [0] = 1; setting this bit initiates the data transfer from the buffer register to the EEPROM (writing process); it is reset by the IC master after the data transfer is done.
Rev. 0 | Page 74 of 80
AD9520-5 APPLICATIONS INFORMATION
FREQUENCY PLANNING USING THE AD9520
The AD9520 is a highly flexible PLL. When choosing the PLL settings and version of the AD9520, the following guidelines should be kept in mind. The AD9520 has four frequency dividers: the reference (or R) divider, the feedback (or N) divider, the VCO divider, and the channel divider. When trying to achieve a particularly difficult frequency divide ratio requiring a large amount of frequency division, some of the frequency division can be done by either the VCO divider or the channel divider, thus allowing a higher phase detector frequency and more flexibility in choosing the loop bandwidth. Choosing a nominal charge pump current in the middle of the allowable range as a starting point allows the designer to increase or decrease the charge pump current and, thus, allows the designer to fine-tune the PLL loop bandwidth in either direction. ADIsimCLK is a powerful PLL modeling tool that can be downloaded from www.analog.com and is a very accurate tool for determining the optimal loop filter for a given application.
SNR (dB)
110 100 90 80 70 60 50 40 30 10 1 SNR = 20log 2f t AJ 18 16
200 fs tJ = 400 fs tJ = 1ps tJ = 2ps
tJ = 100 fs tJ =
14 12 10 8
tJ = 10p
s
6
07239-044
100
1k
fA (MHz)
Figure 57. SNR and ENOB vs. Analog Input Frequency
See the AN-756 Application Note and the AN-501 Application Note at www.analog.com. Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sampling clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment. The differential LVPECL outputs of the AD9520 enable clock solutions that maximize converter SNR performance. The input requirements of the ADC (differential or singleended, logic level termination) should be considered when selecting the best clocking/converter solution.
USING THE AD9520 OUTPUTS FOR ADC CLOCK APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of the sampling clock of the AD9520. An ADC can be thought of as a sampling mixer, and any noise, distortion, or time jitter on the clock is combined with the desired signal at the analog-todigital output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at 14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR can be expressed approximately by
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9520 provide the lowest jitter clock signals available from the AD9520. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 41 shows the LVPECL output stage. In most applications, a LVPECL far-end Thevenin termination (see Figure 58) or Y-termination (see Figure 59) is recommended. In both cases, VS of the receiving buffer should match VS_DRV. If it does not match, ac coupling is recommended (see Figure 60). LVPECL Y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. Even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers limited flexibility for varying the drive strength of the emitter-follower LVPECL driver. This can be an important consideration when driving long trace lengths but is usually not an issue. In the case where VS_DRV = 2.5 V, the 50 termination resistor connected to ground in Figure 59 should be changed to 19 .
1 SNR(dB) = 20 log 2f t AJ

where: fA is the highest analog frequency being digitized. tJ is the rms jitter on the sampling clock. Figure 57 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB).
Rev. 0 | Page 75 of 80
ENOB
AD9520-5
Thevenin-equivalent termination uses a resistor network to provide 50 termination to a dc voltage that is below VOL of the LVPECL driver. In this case, VS_DRV on the AD9520 should equal VS of the receiving buffer. Although the resistor combination shown results in a dc bias point of VS_DRV - 2 V, the actual common-mode voltage is VS_DRV - 1.3 V because there is additional current flowing from the AD9520 LVPECL driver through the pull-down resistor. The circuit is identical for the case where VS_DRV = 2.5 V, except that the pull-down resistor is 62.5 and the pull-up is 250 .
VS_DRV VS_DRV 50 SINGLE-ENDED (NOT COUPLED) 50
07239-045
When single-ended CMOS clocking is used, some of the following guidelines apply. Point-to-point connections should be designed such that each driver has only one receiver, if possible. Connecting outputs in this manner allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the output trace. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. The value of the resistor is dependent on the board design and timing requirements (typically 10 to 100 is used). CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and signal integrity.
07239-076
127
127
VS
LVPECL
LVPECL
83
83
CMOS
10
60.4 (1.0 INCH) CMOS MICROSTRIP
Figure 58. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
VS_DRV Z0 = 50 LVPECL Z0 = 50 50 VS = VS_DRV
Figure 61. Series Termination of CMOS Output
50
07239-047
50
LVPECL
Figure 59. DC-Coupled 3.3 V LVPECL Y-Termination
VS_DRV 0.1nF 100 DIFFERENTIAL 100 (COUPLED) 0.1nF TRANSMISSION LINE 200 VS
Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9520 do not supply enough current to provide a full voltage swing with a low impedance resistive, farend termination, as shown in Figure 62. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets.
VS 100 CMOS 100
07239-077
LVPECL
LVPECL
CMOS
07239-046
10
50
200
Figure 60. AC-Coupled LVPECL with Parallel Transmission Line
Figure 62. CMOS Output with Far-End Termination
CMOS CLOCK DISTRIBUTION
The output drivers of the AD9520 can be configured as CMOS drivers. When selected as a CMOS driver, each output becomes a pair of CMOS outputs, each of which can be individually turned on or off and set as inverting or noninverting. These outputs are 3.3 V or 2.5 V CMOS compatible. However, every output driver (including the LVPECL drivers) must be run at either 2.5 V or 3.3 V. The user cannot mix and match 2.5 V and 3.3 V outputs.
Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9520 offers LVPECL outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.
Rev. 0 | Page 76 of 80
AD9520-5 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
48 49 64 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 8.75 BSC SQ 0.50 BSC EXPOSED PAD
(BOTTOM VIEW)
6.35 6.20 SQ 6.05
0.50 0.40 0.30 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
33 32
16 17
7.50 REF
0.25 MIN
1.00 0.85 0.80
SEATING PLANE
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 63. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad CP-64-4 Dimensions shown in millimeters
ORDERING GUIDE
Model AD9520-5BCPZ 1 AD9520-5BCPZ-REEL71 AD9520-5/PCBZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 77 of 80
091707-C
Package Option CP-64-4 CP-64-4
AD9520-5 NOTES
Rev. 0 | Page 78 of 80
AD9520-5 NOTES
Rev. 0 | Page 79 of 80
AD9520-5 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07239-0-10/08(0)
Rev. 0 | Page 80 of 80

▲Up To Search▲

Price & Availability of AD9520-5

	To Download AD9520-5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .